Memory system for a Doppler radar incorporating a fast Fourier transform computer

• US 4,266,279 A
• Filed: 03/29/1979
• Issued: 05/05/1981
• Est. Priority Date: 03/29/1979
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hines, Kenneth W.
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US06/025,313
• Time in Patent Office: 768 Days
• Field of Search: 364/724, 364/726, 364/900, 343/5 CF, 343/5 DP, 343/5 FT, 343/9 R
• US Class Current: 708/404
• CPC Class Codes: G01S 13/50 Systems of measurement based on relative movement of target
• CPC Class Codes: G01S 7/2806 Employing storage or delay devices which preserve the pulse form of the echo signal, e.g. for comparing and combining echoes received during different periods
• CPC Class Codes: G06F 17/142 Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

Abstract

A data record memory system for use with a Doppler radar incorporating a fast Fourier transform computer wherein the memory system utilizes a single memory constructed to read out and write in data at each address and the data supplied to the memory is sequenced so that the data is read out of the memory system in numerical range bin order.

Claims

1. A fast Fourier transform computer with a predetermined radix utilized in conjunction with a Doppler radar and incorporating a data record memory system for receiving and storing a batch of data, a batch of data including a predetermined number of radar samples and a substantially larger predetermined number of range bins per sample, and reading out the stored batch of data in numercial range bin order, said memory system comprising:

(a) a random access memory being sufficiently large to store a batch of data and connected to write data for storage and substantially simultaneously read output data at each selected address of said memory;

(b) data sequencing circuitry for receiving data from the radar and supplying the data to the random access memory in a predetermined sequence; and

(c) address selection means connected to said random access memory for selecting the addresses therein in a sequence that operates in conjunction with the predetermined sequence of received data to read data out in numerical range bin order.

2. A memory system as claimed in claim 1 wherein the data sequencing circuitry includes random access memory means and an address generator for storing the data and supplying the data at an output in the predetermined sequence.

3. A memory system as claimed in claim 2 wherein the random access memory means includes two random access memories and switching means connected to alternately write data into one memory while stored data is read out of the other memory.

4. A memory system as claimed in claim 3 wherein data from the Doppler radar is written into one of the memories in the order it is received and read out of the other memory in the predetermined sequence dictated by the address generator.

5. A memory system as claimed in claim 2 wherein the address generator includes clock means providing clock pulses at a predetermined frequency, first means for providing an output signal equal to the clock pulses divided by a number equal to the radix of the computer, second means connected to provide an output signal equal to the output signal of said first means divided by the ratio of samples to the radix, third means connected to provide an output signal equal to the output signal of said second means divided by the ratio of range bins to samples, fourth means connected to provide an output signal equal to the sum of the output signal of said first means multiplied by the ratio of range bins to the radix and the output signal of said second means multiplied by the ratio of range bins to samples, and fifth means connected to provide an address signal equal to the sum of the output signals of said third means and said fourth means.

6. A memory system as recited in claim 1 wherein the address selection means includes a first address generator for providing the sequence of reading/writing alternate batches of data and a second address generator for providing the sequence of reading/writing the remaining batches of data, said first address generator being programmed to read/write by columns and said second address generator being programmed to read/write by rows.

7. A memory system as claimed in claim 6 wherein the first address generator includes clock means providing clock pulses at a predetermined frequency, first means for providing an output signal equal to the clock pulses divided by a number equal to the radix of the computer, second means connected to provide an output signal equal to the output signal of said first means divided by the ratio of samples to the radix, third means connected to provide an output signal equal to the output signal of said second means divided by the ratio of range bins to samples, fourth means connected to provide an output signal equal to the output signal of said third means divided by the ratio of samples to the radix, fifth means connected to provide an output signal equal to the output signal of said fourth means divided by a number equal to the radix of the computer, sixth means connected to provide an output signal equal to the sum of the output signal of said second means multiplied by the ratio of range bins to the radix and the output signal of said third means multiplied by the ratio of samples to the radix, seventh means connected to provide an output signal equal to the sum of the output signals of said sixth means and said fourth means, eighth means connected to provide an output signal equal to the sum of the output of said first means multiplied by a number equal to the ratio of the product of range bins and samples to the radix and the output of said seventh means, and ninth means connected to provide an output signal equal to the sum of the output of said fifth means multiplied by a number equal to the ratio of the product of range bins and samples to the square of the radix and the output of said eighth means.

8. A memory system as claimed in claim 6 wherein the second address generator includes clock means providing clock pulses at a predetermined frequency, first means for providing an output signal equal to the clock pulse divided by a number equal to the radix of the computer, second means connected to provide an output signal equal to the output signal of said first means divided by the ratio of the product of range bins and samples to the square of the radix, third means connected to provide an output signal equal to the output signal of said second means divided by a number equal to the radix of the computer, fourth means connected to provide an output signal equal to the sum of the output of said first means multiplied by a number equal to the ratio of the product of range bins and samples to the square of the radix and the output of said second means, and fifth means connected to provide an output signal equal to the sum of the output of said third means multiplied by a number equal to the ratio of the product of range bins and samples to the radix and the output of said fourth means.