Copy reproduction machine with controller self check system

• US 4,266,294 A
• Filed: 04/09/1979
• Issued: 05/05/1981
• Est. Priority Date: 08/30/1977
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Daughton, John W., Wilczek, Stephen P., Steiner, Edward L.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/028,480
• Time in Patent Office: 757 Days
• Field of Search: 371/22, 371/24, 371/71, 364/900, 355/14, 179/175.31 R
• US Class Current: 714/735
• CPC Class Codes: G03G 15/55 Self-diagnostics; Malfunction or lifetime display
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

An electrostatographic type copying or reproduction machine incorporating a programmable controller to operate the various machine components in an integrated manner to produce copies is disclosed. The controller carries a master program bearing machine operating parameters from which an operating program for the specific copy run desired is formed and used to operate the machine components to produce the copies programmed. A multiple prioritized interrupt system is employed to distribute the operating program to the machine.

Self check routines check the operational integrity of the controller prior to start-up of the machine and periodically while the machine is processing copies.

Claims

1. In an electrophotographic machine with a plurality of processing elements and with a controller having a CPU and a plurality of control modules, the controller having address and data lines for identifying a particular processing element of the electrophotographic machine and providing data flow with the particular processing element identified, the address and data lines interconnecting the CPU, the control modules, and the processing elements, the method of verifying the integrity of one of said address and data lines associated with one of said plurality of control modules comprising the steps of:

looping a test bit through one of the address and data lines, between the CPU and a first one of the plurality of control modules,

reading the bit returned,

comparing the returned bit with the test bit sent,

looping a test bit through one of the address and data lines between the CPU, the first one of the plurality of control modules, and the second one of the plurality of control modules, reading the bit returned and comparing the bit returned with the test bit sent and

declaring a fault when the returned bit differs from the test bit.

2. The method of claim 1 wherein the control modules are disposed intermediate the CPU and the processing elements of the electrophotographic machine including the step of verifying the integrity of the data lines associated with the control modules between the CPU and the processing elements.

3. The method of claim 1 including the step of determining the particular control module causing a malfunction.

4. In an electrophotographic printing machine having a plurality of machine processing elements and a controller having a CPU module, an input-output module electrically connected to the CPU module, and an interface module electrically connected to the input-output module and to the machine processing elements, the controller having address and data lines for communicating with the machine processing elements, the address and data lines interconnecting the CPU module, the input-output module and the interface module, the method of verifying the integrity of the input-output and interface modules comprising the steps of

looping a test bit from the CPU module to the input-output module and back to the CPU module

driving a test bit between the interface module and the input-output module and storing manifestations of failed bits,

looping a test bit from the CPU module through the input-output module to the interface module and back through the input-output module to the CPU module and

determining failure of either the input-output module or the interface module.

5. The method of claim 4 including the steps of sending a test bit on the address lines between the CPU module and the input-output module and returning said bit to the CPU module on the data lines from the input-output module to the CPU module,

sending a test bit on the address lines from the CPU module through the input-output module to the interface module and from the interface module to the CPU module on the data line from the interface module to the CPU module.

6. In an electrophotographic machine with a controller having a CPU module and an input-output module, the controller having address and data lines for identifying a particular processing element of the electrophotographic machine and providing data flow with the particular processing element addressed, the method of verifying the integrity of one of said address or data lines comprising the steps of:

looping a test bit through said lines,

reading the bit returned, comparing the returned bit with the test bit, and

declaring a fault when the return signal differs from the test signal,

including the steps of;

(a) sending a test bit on the data lines from the CPU to the input-output module and returning the test bit from the input-output module to the CPU module for all possible combinations of data on the data lines,

(b) sending the test bit on the address lines from the CPU module to the input-output module and returning the test signals from the input-output module to the CPU module over the data lines for all possible combinations of data on the address lines.

7. The method of claim 6 wherein the controller contains an interface module, the input-output module being disposed between the CPU module and the interface module, comprising the steps of:

driving predetermined bits from the interface module to the input-output module, comparing the predetermined driven bits with the received bits, and

storing the manifestation of any errors.