Acquisition delay circuit for a PLL reference oscillator
First Claim
1. In a PLL synthesizer tuning system for generating frequencies according to the desired channel of operation, said system having a reference oscillator selectively operable either in a crystal-controlled, injection-locked mode or in a voltage-controlled, mode, wherein the reference oscillator operating frequency is determined by a tuning voltage applied to a tuning voltage control terminal of said oscillator, alternatively supplied said toning voltage either by a manually-variable fine tuning circuit or by an AFC control circuit, and having a control circuit for determining the mode of operation of the reference oscillator, an acquisition delay circuit for assuring PLL acquisition in the voltage-conrolled mode, said delay circuit comprising:
- a monostable having a trigger input responsive to edges of trigger pulses of a particular polarity and an output coupled to the control circuit, anda trigger network coupled to the trigger input, said network including means for triggering the monstable in response to a change in the synthesizer'"'"'s channel of operation.
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Accused Products
Abstract
A delay circuit for enhancing acquisition of a synthesizer PLL subsequent to change in the synthesizer'"'"'s frequency of operation or a change in the source of tuning voltage applied to a voltage-controllable reference oscillator. A control circuit determines whether the reference oscillator operates in a crystal-controlled or in a voltage-controlled mode. The delay circuit includes a monostable having an output coupled to the control circuit and a trigger input coupled to both an ENTER CHANNEL indicator and a pulse generator. The monostable is triggered, thereby assuring temporary crystal-controlled operation of the reference oscillator, in response to an ENTER CHANNEL indicator or to an output from a pulse generator. The pulse generator is responsive to a change in the source of reference oscillator tuning control voltage from, for example, a manually variable fine tuning potentiometer to an AFC control circuit.
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Citations
18 Claims
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1. In a PLL synthesizer tuning system for generating frequencies according to the desired channel of operation, said system having a reference oscillator selectively operable either in a crystal-controlled, injection-locked mode or in a voltage-controlled, mode, wherein the reference oscillator operating frequency is determined by a tuning voltage applied to a tuning voltage control terminal of said oscillator, alternatively supplied said toning voltage either by a manually-variable fine tuning circuit or by an AFC control circuit, and having a control circuit for determining the mode of operation of the reference oscillator, an acquisition delay circuit for assuring PLL acquisition in the voltage-conrolled mode, said delay circuit comprising:
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a monostable having a trigger input responsive to edges of trigger pulses of a particular polarity and an output coupled to the control circuit, and a trigger network coupled to the trigger input, said network including means for triggering the monstable in response to a change in the synthesizer'"'"'s channel of operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In a PLL synthesizer having a reference oscillator alternately operable in either a crystal-controlled mode or in a voltage-controlled mode as determined by a control circuit having an output coupled to the reference oscillator and, where in the voltage-controlled mode, the reference oscillator is selectively controllable by one of at least either a first or a second source of tuning voltage as selected by voltage applying means coupled between a reference oscillator tuning control terminal and the sources of tuning voltage, an acquisition delay circuit for enhancing PLL acquisition subsequent to a selection in the source of tuning voltage, the acquisition delay circuit comprising:
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switching means coupled to the voltage applying means for detecting and indicating a selection in the source of tuning voltage, a pulse generator having an input coupled to the switching means, and a monostable having a trigger input coupled to an output of the pulse generator and an output coupled to the input of the control circuit, so that subsequent to a selection in the source of tuning voltage the pulse generator develops an output pulse thereby triggering the monostable and assuring that the reference oscillator operates in the crystal-controlled mode for a period of time equivalent to the monostable output pulse duration. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An acquisition delay circuit for a voltage-controllable PLL reference oscillator including a controllable tuning control terminal at which is applied a voltage as selected from a plurality of sources of tuning voltage by a voltage applying means, said circuit comprising:
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a monostable, a trigger network coupled to the input of the monostable, switching means coupled to the voltage applying means, said switching means for detecting and indicating a selection in the source of tuning voltage, and a pulse generator having an input coupled to the switching means and an ouput coupled to the trigger network for triggering the monstable subsequent to a change in the source of tuning voltage. - View Dependent Claims (18)
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Specification