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Interruption control method for multiprocessor system

  • US 4,268,904 A
  • Filed: 12/13/1978
  • Issued: 05/19/1981
  • Est. Priority Date: 02/15/1978
  • Status: Expired due to Term
First Claim
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1. In a multiprocessor system formed of a plurality of microprocessors and including a shared memory unit, a method for controlling the processing of an interrupt command issued by an I/O device electrically interconnected with said microprocessors comprising the steps of:

  • entering into the general register of each of said microprocessors a program status word including a priority order designating code indicating the relative priority in which said microprocessor is assigned to accept interrupt commands;

    storing in said shared memory unit a plurality of entry addresses at locations dedicated to said individual microprocessors and addressable in terms of said priority order designating code;

    selecting, in accordance with the priority order defined by said priority order designating code, one of said microprocessors to process an interrupt-servicing program in response to an interrupt command;

    addressing said main memory unit at the entry address data location corresponding to the priority order designating code of said selected microprocessor; and

    loading into the general register of said selected microprocessor entry address data obtained from said addressed entry address data location to enable said microprocessor to access a stored interrupt-servicing program for processing said interrupt command.

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