Interruption control method for multiprocessor system

• US 4,268,904 A
• Filed: 12/13/1978
• Issued: 05/19/1981
• Est. Priority Date: 02/15/1978
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Inventors: Suzuki, Seigo, Eguchi, Seiji
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/969,008
• Time in Patent Office: 888 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/40
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to determine which processor will respond to the interrupt command. The processors are arranged in a fixed priority sequence and respond to an interrupt command in a designated priority order. Controls are provided to prevent a processor which is executing an interrupt-servicing program from responding to a subsequent interrupt command until execution of the interrupt-servicing program is completed.

Claims

1. In a multiprocessor system formed of a plurality of microprocessors and including a shared memory unit, a method for controlling the processing of an interrupt command issued by an I/O device electrically interconnected with said microprocessors comprising the steps of:

entering into the general register of each of said microprocessors a program status word including a priority order designating code indicating the relative priority in which said microprocessor is assigned to accept interrupt commands;

storing in said shared memory unit a plurality of entry addresses at locations dedicated to said individual microprocessors and addressable in terms of said priority order designating code;

selecting, in accordance with the priority order defined by said priority order designating code, one of said microprocessors to process an interrupt-servicing program in response to an interrupt command;

addressing said main memory unit at the entry address data location corresponding to the priority order designating code of said selected microprocessor; and

loading into the general register of said selected microprocessor entry address data obtained from said addressed entry address data location to enable said microprocessor to access a stored interrupt-servicing program for processing said interrupt command.

2. The method set forth in claim 1 wherein an interrupt command is encoded to represent a plurality of different interrupt levels and comprising the further steps of:

storing in the entry address data location dedicated to each individual microprocessor a number of entry address data words corresponding to the number of different interrupt levels that can be represented by said interrupt by said interrupt command; and

accessing during said addressing step the entry address data word corresponding to the interrupt level represented by said interrupt command to enable accessing of a stored interrupt-servicing program as designated by said encoded interrupt command.

3. The method set forth in claim 2 comprising the further step of:

transferring, prior to said loading step, the contents of the general register of said selected microprocessor to a storage location in said main memory to preserve said general register contents for subsequent resumption of processing of the program being executed by said selected processor at the time of said interrupt command.