Transceiver for phase-shift modulated carrier signals

• US 4,270,206 A
• Filed: 02/25/1980
• Issued: 05/26/1981
• Est. Priority Date: 02/25/1980
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hughes, William C.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/124,347
• Time in Patent Office: 456 Days
• Field of Search: 375/9, 375/52, 375/57, 375/58, 375/106, 375/114, 455/76, 455/73, 370/100, 370/12, 340/310 R, 340/310 A, 179/2 DP
• US Class Current: 375/223
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence

Abstract

A transceiver for a phase-shift-modulated carrier data communications system, includes a digital-data-recovering receiver having relatively wide band-pass filters and a complimentary integrate-and-dump data detector. A pseudo-bandpass-filtered, modulated-carrier synthesizer provides a transmission signal, under control of a frequency-arithmetic multiple-frequency synthesizer, which is also utilized to provide all required frequencies to the receiver mixers and band synchronization circuitry. All transceiver frequencies are locked to the instantaneous frequency of a system-wide signal.

Claims

1. A transceiver for use in a system communicating digital data over a preselected transmission medium by phase-shift-modulation of a carrier waveform having a frequency related to the frequency of a system-wide waveform, comprising:

a transmitter section having an input receiving a clock frequency waveform, another input receiving a transmit clock waveform and an output, and including means for synthesizing a pseudo-bandpass-filtered waveform having said carrier frequency, responsive to receipt of said clock frequency waveform;

means receiving at least one bit of digital data to be transmitted for storing said data and for sequentially providing each successive data bit at an output thereof responsive to an associated one of successive portions of said transmit clock waveform;

means receiving the at least one data bit from said storing means output for modulating the phase shift of the carrier frequency waveform responsive to the digital value of the data bit to be then transmitted; and

means for amplifying the amplitude of the phase-shift-modulated, pseudo-bandpass-filtered carrier frequency waveform and coupling the amplified carrier waveform to said transmitter section output;

a receiver section having an received carrier input, a reference signal input and a recovered data output, said receiver section including means connected to said received carrier and reference signal inputs for providing a baseband data signal having each of a plurality of amplitude transitions thereof responsive to an associated reversal of the phase of the waveform of said received carrier;

means receiving said baseband data signal for generating a baud synchronization signal having periodic amplitude transitions synchronized to the transitions of said baseband data signal; and

means receiving said baud synchronization and baseband data signals for recovering the digital data modulated onto said received carrier waveform, and providing said recovered digital data at said receiver section recovered data output;

means for generating said transmit clock waveform with a preselected frequency and phase relationship to the waveform of said baud synchronization signal; and

a frequency synthesizer section having an input receiving said system-wide waveform and including means for generating said clock frequency waveform for said transmitter section; and

means for generating said reference signal for said receiver section.

2. The transceiver as set forth in claim 1, wherein said reference signal generating means includes:

means for providing a first reference waveform having zero crossings coincident with the zero crossings of the system-wide waveform;

first phase detector means receiving said first reference waveform and a first loop waveform for providing an output signal having an amplitude responsive to the phase difference between said first reference and first loop waveforms;

oscillator means for generating a waveform having a frequency greater than the frequency of the waveform of said reference signal;

pulse-swallower means for subtracting transitions from said oscillator means waveform to provide the waveform of said reference signal having a preselected number of transitions per second, the number of transitions subtracted from said oscillator means waveform being established responsive to the amplitude of said first phase detector means output signal;

frequency-arithmetic means for providing a second reference waveform having a transition frequency equal to a first integer multiple of said system-wide waveform frequency;

second phase detector means receiving said second reference waveform and a second loop waveform for providing an output signal having an amplitude responsive to the phase difference between said second reference and second loop waveforms;

means for generating an essentially square waveform having a frequency responsive to the amplitude of said second phase detector output signal and which square waveform frequency is a second integer multiple of said system-wide waveform frequency; and

means for dividing the frequency of said output square waveform of said generating means by said second integer multiple to provide the first loop waveform to said first phase detector means and also for dividing said waveform generating means output waveform frequency by first integer multiple to provide said second loop waveform to said second phase detector means.

3. The transceiver as set forth in claim 2, wherein said clock frequency waveform generating means includes means for dividing said generating means output square waveform by a third integer multiple to provide the clock frequency waveform to said transmitter section.

4. The transceiver as set forth in claim 2, wherein said first phase detector means includes means for low-pass filtering the output signal thereof.

5. The transceiver as set forth in claim 2, wherein said pulse-swallower means includes:

a flip-flop logic element having a true Q output and an inverted Q output, a data input and a clock input receiving the oscillator means waveform, the logic states of said Q and Q outputs being complimentary and controlled by the signal at said data input being greater than or less than a data input threshold voltage when a preselected polarity transition of the oscillator means waveform occurs at said clock input;

means for integrating the first phase detector means output signal to apply a voltage to said data input of said flip-flop logic element;

a first unidirectionally-conducting device having an anode connected to said data input and a cathode connected to said Q output;

a second unidirectionally-conducting device having an anode connected to said Q output and a cathode; and

a resistance element connected between the second device cathode and said clock input;

said reference signal waveform being provided at said second device cathode.

6. The apparatus as set forth in claim 2, wherein said oscillator means includes a crystal element for controlling the frequency thereof.

7. The transceiver as set forth in claim 2, wherein said frequency-arithmetic means includes:

first frequency divider means for providing a waveform having a number of transitions per second which is an integer sub-multiple of the number of transitions per second of said reference signal waveform;

first frequency adder means for providing an output waveform having a number of transitions per second equal to the sum of the transitions per second of said first frequency divider means waveform plus the number of transitions per second of another waveform;

second frequency divider means for providing an output waveform having a number of transitions per second which is an integer submultiple of the first frequency adder means output waveform, said second frequency divider means output waveform being said another waveform applied to said first frequency adder means; and

second frequency adder means for providing an output waveform having a number of transitions per second equal to the sum of the number of transitions per second of said first frequency adder means output waveform plus the number of transitions per second of said reference signal waveform.

8. The transceiver as set forth in claim 7, wherein at least one of said integer sub-multiples for said reference signal and first adder means waveforms is by division of that waveform by an integer power of base 2.

9. The transceiver as set forth in claim 7, further including third frequency divider means for providing an output waveform having a number of transitions per second which is another integer submultiple of the number of transitions per second of the output waveform of said second frequency adder means, the output waveform of the third frequency divider means being said second reference waveform.

10. The transceiver as set forth in claim 7, further comprising first means for delaying transitions of said second frequency divider means output waveform to cause the transitions of said first and second frequency divider means output waveforms to occur at different times at said first frequency adder means.

11. The transceiver as set forth in claim 7, further including second means for delaying transitions of said reference signal waveform to cause the transitions of said reference signal and said first frequency adder means output waveforms to occur at different times at said second frequency adder means.

12. The transceiver as set forth in claim 2, wherein said square waveform generating means includes a voltage-controlled oscillator having said square waveform at an output thereof at a frequency responsive to the magnitude of a voltage at a control input;

and means for low-pass filtering the second phase detector means output signal for application to said voltage-controlled oscillator control input.

13. The transceiver as set forth in claim 2, wherein at least one of said first, second and third integer multiples is by multiplication by a positive integer power of base 2.

14. The transceiver as set forth in claim 1, wherein the number of baud synchronization signal transitions is one-half of the maximum possible number of baseband data signal transitions, and said digital data recovering means comprises:

first and second integrators each having an input receiving said baseband data signal and an output;

means for alternatingly connecting one of the first and second integrator outputs substantially to ground potential responsive to said baud synchronization signal alternating between first and second logic levels;

a differential amplifier having inverting and noninverting inputs respectively connected to an associated one of the first and second integrator outputs, and having an output at which a signal appears with amplitude responsive to the amplitude of the integrated baseband data signal and with polarity established by the connection to substantially ground potential of the remaining one of said first and second integrator means outputs;

means having a first input receiving the output of said amplifier and having a second input receiving said baud synchronization signal for selectively inverting the amplifier output signal amplitude when said baud synchronization signal is at that one of said first and second logic levels causing said amplifier to provide the output signal thereof with a negative polarity; and

means for low-pass filtering the output of said inverting means to provide the recovered digital data signal at the receiver section recovered data output.

15. The transceiver as set forth in claim 14, wherein said first and second integrators are resistance-capacitance integration networks.

16. The transceiver is set forth in claim 1, wherein said baud synchronization signal generating means comprises phase detector means receiving said baseband data signal and a local clock waveform for providing an output signal having an amplitude responsive to the phase difference therebetween;

a voltage-controlled oscillator having a control input and an output at which a square waveform is generated with frequency established by the magnitude of a signal at said control input;

counter means receiving the output waveform of said voltage-controlled oscillator for providing said local clock waveform, said baud synchronization signal and a third signal respectively at first, second and third integer submultiples of said voltage-controlled oscillator output waveform frequency;

another phase detector means receiving said voltage-controlled oscillator output waveform and a synchronization waveform which is an integer multiple of said clock frequency waveform applied to said transmitter section, for providing an output waveform having an amplitude responsive to the phase difference therebetween;

frequency adder means for providing an output waveform having a frequency equal to the sum of the frequencies of said another phase detector output waveform and the counter means third signal waveform; and

means receiving the output waveforms from said first phase detector means and from said frequency adder means for providing a voltage to said voltage-controlled oscillator control input to cause said baud synchronization signal to have transitions concurrent with the transitions of said baseband data signal.

17. The transceiver as set forth in claim 16, wherein said baud synchronization signal generating means further includes means connected to said frequency adder means for preventing the application of said counter means third signal waveform thereto only when said transceiver is transmitting digital data.

18. The transceiver as set forth in claim 17, wherein said counter means also provides a fourth output waveform at a fourth integer submultiple of said voltage-controlled oscillator output waveform frequency;

and said transmit clock waveform generating means includes Johnson counter means receiving said counter means fourth output waveform at a clock input thereof and the inverse of said local clock waveform at a reset input thereof for providing, during one-half of the total time interval of said local clock signal, a plurality D of mutually-exclusive outputs each at a frequency D times less than the frequency of said counter means fourth output waveform and each present in mutually exclusive manner with respect to all of the remaining outputs of said Johnson counter;

a selected one of said D outputs being said transmit clock waveform for connection to said transmitter section data storing means.

19. The transceiver as set forth in claim 16, wherein said frequency adder is an exclusive-OR gate having a first input receiving the output of said another phase detector means and having a second input receiving said counter means third output waveform, and having an output at which said waveform having a frequency equal to the sum of said input frequencies appears.

20. The transceiver as set forth in claim 16, wherein said another phase detector means is an exclusive-OR gate having a first input receiving the output waveform from said voltage-controlled oscillator and a second input receiving said synchronization waveform at said integer multiple of said clock frequency, and having an output at which said signal of amplitude responsive to the phase difference between the signals at the first and second inputs appears.

21. The transceiver of claim 1, wherein said baseband data signal providing means comprises:

amplifier means for bandpass filtering the carrier waveform received at said receiver section input;

means for generating a first error signal of amplitude responsive to a difference in phase between the bandpass-filtered carrier signal and a first signal at a frequency equal to said carrier frequency;

phase-locked loop means receiving said reference signal waveform from said frequency-synthesizer section and said bandpass-filtered carrier signal for generating said first signal at a frequency locked to said carrier frequency; and

means for low-pass filtering said first error signal to recover said baseband data signal.

22. The transceiver as set forth in claim 21, wherein said phase-locked loop means includes oscillator means receiving said reference signal waveform for generating a square waveform output of frequency controlled by the amplitude of a control signal at an input thereof;

means for selectively inverting the sqaure waveform output of said generating means responsive to the level of said first error signal;

means for generating a second error signal of amplitude responsive to a difference in phase between the selectively inverting means output square waveform and the bandpass-filtered carrier waveform; and

means for low-pass filtering said second error signal to provide said control signal at said generating means control input for locking the frequency of said generating means to the frequency of the received carrier waveform.

23. The transceiver as set forth in claim 22, wherein said oscillator means includes counter means receiving an input waveform at an input frequency for providing a first output signal at a frequency which is a first integer sub-multiple of the input frequency, for connection to said selectively inverting means, and for providing a second output signal having a frequency which is a second integer sub-multiple of said input frequency;

frequency adder means receiving said reference signal waveform, said counter means second output signal and said control input signal for providing to said counter means input a waveform having the frequency of said reference signal when the amplitude of the said error signal at said control input is less than a predetermined level and at a frequency equal to the sum of said reference signal and counter means second output signal frequencies when said control input amplitude is greater than said predetermined level.

24. The transceiver as set forth in claim 23, wherein said frequency adder means comprises a logic gate having a first input receiving said control signal, a second input receiving said counter means second output signal, and an output at which a waveform having the same frequency as the frequency of said counter means second output signal appears only when said control input signal exceeds said predetermined level;

and an exclusive-OR gate having a first input connected to the output of said logic gate, a second input receiving said reference waveform, and an output at which said sum signal appears to connect to the input of said counter means.

25. The transceiver as set forth in claim 22, wherein said selectively inverting means receives the output of said first error signal generating means for providing a logic signal respectively at first and second states responsive respectively to said first error signal having first and second polarities, and an exclusive-OR gate having a first input receiving said counter means first output signal, a second input receiving the output of said level detecting means, and an output at which said selectively inverted output square waveform appears.

26. The transceiver as set forth in claim 22, wherein said second error signal generating means comprises means for inverting the polarity of said bandpass-filtered carrier waveform;

and a linear mixer having first and second inputs respectively receiving the bandpass-filtered carrier waveform and the inverted polarity bandpass-filtered carrier waveform, and having another input receiving said selectively inverting means output square waveform, and an output at which said second error signal appears.

27. The transceiver as set forth in claim 26, wherein said inverting means includes an input, an output and first and second resistance elements of essentially equal magnitude, connected in series between said input and output of said inverting means;

and said second error signal low-pass filtering means is a resistance-capacitance active low-pass filter including an operational amplifier having an inverting input connected to the junction between said first and second resistance elements.

28. The transceiver as set forth in claim 26, wherein said first error signal generating means comprises means for shifting the phase of said phase-locked loop generating means square output waveform by 90°

; and

a linear mixer having first and second inputs respectively receiving the bandpass-filtered carrier waveform and the inverted polarity bandpass-filtered carrier waveform, a control input receiving the 90°

phase-shifted square waveform, and an output at which said first error signal appears.

29. The transceiver as set forth in claim 1, further including means for selectively coupling said transmission medium to said transmitter section output only when data is to be transmitted, and for selectively coupling said transmission medium to said receiver section input at all other times.

30. The transceiver as set forth in claim 1, wherein different frequency carriers are transmitted by said transmitter section and received by said receiver section, and wherein said transceiver is adapted for operation in a full-duplex mode.