Digital compressive receiver

• US 4,270,209 A
• Filed: 12/07/1979
• Issued: 05/26/1981
• Est. Priority Date: 12/07/1979
• Status: Expired due to Term

• Current Assignee: ITT Corporation (ITT, Inc.)
• Original Assignee: International Telephone & Telegraph Corp. (ITT, Inc.)
• Inventors: Albanese, Damian F.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/101,259
• Time in Patent Office: 536 Days
• Field of Search: 375/1, 375/10, 375/96, 375/115, 375/121, 364/485, 364/550, 364/724, 364/728, 324/77 B, 324/77 C, 324/77 G, 324/77 H, 324/77 R, 455/145, 455/146, 455/147, 455/148
• US Class Current: 375/343
• CPC Class Codes: H03H 17/0254 Matched filters
• CPC Class Codes: H03J 7/32 with simultaneous display of received frequencies, e.g. panoramic receivers

Abstract

A compressive receiver for developing a series of time-based identifying pulses corresponding to discrete received signals having various frequencies within a predetermined band of surveillance. A multiple local oscillator function is included, effectively dividing the predetermined band of interest into small frequency increments, each of these local oscillator signals being coded by a pseudo-random coded sequence (bi-phase code) of maximal length. Each frequency increment thus developed is coded by this sequence delayed by one bit duration as compared to that applied to the local oscillator frequency immediately preceding it. A mixer receiving input signals in the band of interest, and also the multiple local oscillator signals thus generated and coded, has its output processed by a passive correlator which provides pulses at times determined by the frequencies extant in the input signal.

Claims

1. A compressive surveillance receiver, comprising:

frequency synthesizing means for generating a composite local oscillator signal including N discrete signal uniformly spaced in frequency;

first means for generating a repetitive digitally coded sequence having N bits;

second means responsive to said first means for providing N outputs, said coded sequence appearing at each of said N outputs in a delayed series whereby said coded sequence is extant at each successive output of said series delayed by one bit as compared to the preceding output in said series;

third means for modulating each of said N discrete local oscillator signals by said coded sequence extant at a corresponding one of said N outputs of said second means to provide N modulated outputs;

mixer means responsive to received input signals in a band of surveillance and to said third means outputs for converting said received input signals to signals in the intermediate frequency domain;

and means comprising a matched filter responsive to said intermediate frequency signals for correlating all coded sequence modulated intermediate frequency signals extant at the output of said mixer and corresponding to said received input signals to provide output pulses at times which are a function of the corresponding delay of the coded sequence modulated onto each corresponding local oscillator signal generated by said frequency synthesizer.

2. A receiver according to claim 1 in which an intermediate frequency band-pass filter is included between said mixer and said matched filter, said filter having a pass band substantially equal to the predetermined band of frequencies of said surveillance.

3. A receiver according to claim 2 in which a preselection filter having substantially the same pass band as said intermediate frequency band-pass filter is included in the input signal path preceding said mixer.

4. A receiver according to claim 1 in which said matched filter comprises a delay line having a length in terms of time equal to the duration of said coded sequence and having N taps spaced by a time equal to the bit duration of said coded sequence, said matched filter also including a summer responsive to said N taps to produce a pulse corresponding to the correlation peak produced for each of said coded sequences, the output of said summer thereby providing a group of said pulses spaced along a time base and each analogous to the frequency of a corresponding received input signal.

5. Apparatus according to claim 2 including a preselector in the signal path ahead of said mixer means, said preselector having substantially the same bandwidth as said intermediate frequency band-pass filter.

6. Apparatus according to claim 4 including a preselector in the signal path ahead of said mixer means, said preselector having substantially the same bandwidth as said intermediate frequency band-pass filter.

7. A system according to claim 1 in which said matched filter comprises a delay device having a total delay equal to the duration of said coded sequence, N taps successively spaced one bit duration along said delay device and a bank of N fixed phase shifters connected one to each of said taps, said phase shifters being distributed in a pattern duplicating the phase sequence in each word of said coded sequence to provide correlation whenever a code word fills said delay device, N being the number of bits in a word of said coded sequence.

8. A system according to claim 7 in which said phase shifters as a group provide N outputs and in which a summer is provided responsive to said N phase shifter outputs, the output of said summer providing a correlation peak whenever said code word fills said delay device.

9. A system according to claim 8 in which said delay device is defined as a delay line.

10. A system according to claim 1 in which said first means comprises a pseudo-random sequence generator providing a maximal length sequence.

11. A system according to claim 10 in which said second means comprises a delay shift register responsive to said first means and said N outputs are taken from a corresponding series of taps, one from each stage of said register, thereby to provide said series of codes delayed by one bit each from the preceding output.

12. A system according to claim 8 in which said first means comprises a pseudo-random sequence generator providing a maximal length sequence and said second means comprises a shift register responsive to said first means for providing said N outputs each delayed one bit duration from the preceding output.