Scan converter utilizing discrete differentially coded signals
First Claim
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1. A scan rate converter, comprising:
- (A) input section means operable in both a fast scan conversion and a slow scan conversion mode, said input section means for;
(1) sampling an input FSTV signal at a fast scan rate when said input section means is operated in said fast scan conversion mode, said input FSTV signal including a plurality of lines of video information;
(2) sampling an input SSTV signal at a slow scan rate when said input section means is operated in said slow scan conversion mode, said input SSTV signal including a plurality of lines of video information; and
(3) generating a discrete differential coded signal responsive to each said sampling of said input FSTV and input SSTV signals when said input section means is operated in said fast scan and slow scan modes of operation, respectively, such that each line of video information being sampled is divided into a plurality of discrete differential coded signals, each of said discrete differential coded signals having a magnitude determined by the difference between the actual magnitude of the FSTV or SSTV signal being sampled at the sampling instant corresponding to the discrete differential coded signal in question and a predicted magnitude of the FSTV or SSTV signal being sampled at the sampling instant corresponding to the discrete differential coded signal in question, the value of said predicted magnitude of the FSTV or SSTV signal being sampled being reset to a predetermined value at each sampling instant corresponding to the first discrete differential coded signal in a line of video information being sampled,(B) memory section means operable in a read and a write mode of operation, said memory section means for;
(1) storing each of said discrete differential coded signals generated by said input section means when said memory section means is operated in said write mode; and
(2) reading said discrete differential coded signals stored in said memory section means out of said memory section means when said memory section means is operated in said read mode, said discrete differential coded signals stored in said memory section means being read out of said memory section means at both said fast scan and said slow scan sampling rates in a time multiplexed manner; and
(C) output section means for;
(1) converting said discrete differential coded signals read out of said memory section means at said fast scan rate into an output FSTV signal; and
(2) converting said discrete differential coded signals read out of said memory section means at said slow scan rate into an output SSTV signal.
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Abstract
A scan rate converter utilizing a discrete differential coding system as disclosed. The scan rate converter converts input FSTV and SSTV video information into discrete differential coded signals and stores these signals in a high speed memory. The stored video information is read out of the high speed memory at both a fast scan and a slow scan rate and is reconverted into respective FFST and SSTV output signals.
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Citations
14 Claims
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1. A scan rate converter, comprising:
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(A) input section means operable in both a fast scan conversion and a slow scan conversion mode, said input section means for; (1) sampling an input FSTV signal at a fast scan rate when said input section means is operated in said fast scan conversion mode, said input FSTV signal including a plurality of lines of video information; (2) sampling an input SSTV signal at a slow scan rate when said input section means is operated in said slow scan conversion mode, said input SSTV signal including a plurality of lines of video information; and (3) generating a discrete differential coded signal responsive to each said sampling of said input FSTV and input SSTV signals when said input section means is operated in said fast scan and slow scan modes of operation, respectively, such that each line of video information being sampled is divided into a plurality of discrete differential coded signals, each of said discrete differential coded signals having a magnitude determined by the difference between the actual magnitude of the FSTV or SSTV signal being sampled at the sampling instant corresponding to the discrete differential coded signal in question and a predicted magnitude of the FSTV or SSTV signal being sampled at the sampling instant corresponding to the discrete differential coded signal in question, the value of said predicted magnitude of the FSTV or SSTV signal being sampled being reset to a predetermined value at each sampling instant corresponding to the first discrete differential coded signal in a line of video information being sampled, (B) memory section means operable in a read and a write mode of operation, said memory section means for; (1) storing each of said discrete differential coded signals generated by said input section means when said memory section means is operated in said write mode; and (2) reading said discrete differential coded signals stored in said memory section means out of said memory section means when said memory section means is operated in said read mode, said discrete differential coded signals stored in said memory section means being read out of said memory section means at both said fast scan and said slow scan sampling rates in a time multiplexed manner; and (C) output section means for; (1) converting said discrete differential coded signals read out of said memory section means at said fast scan rate into an output FSTV signal; and (2) converting said discrete differential coded signals read out of said memory section means at said slow scan rate into an output SSTV signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A scan rate converter, comprising:
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(A) input section means operable in both a fast scan conversion and a slow scan conversion mode, said input section means for; (1) sampling an input FSTV signal at a fast scan rate when said input section means is operated in said fast scan conversion mode; (2) sampling an input SSTV signal at a slow scan rate when said input section means is operated in said slow scan conversion mode; and (3) generating a discrete differential coded signal responsive to each said sampling of said input FSTV and input SSTV signals when said input section means is operated in said fast scan and slow scan modes of operation, respectively; (B) memory section means operable in a read and a write mode of operation, said memory section means for; (1) storing each of said discrete differential coded signals generated by said input section means when said memory section means is operated in said write mode; and (2) reading said discrete differential coded signals stored in said memory section means out of said memory section means when said memory section means is operated in said read mode, said discrete differential coded signals stored in said memory section means being read out of said memory section means at both said fast scan and said slow scan sampling rates in a time multiplexed manner; and (C) output section means for; (1) converting said discrete differential coded signals read out of said memory section means at said fast scan rate into an output FSTV signal; and (2) converting said discrete differential coded signals read out of said memory section means at said slow scan rate into an output SSTV signal; (D) said input section means comprising; (1) a discrete differential coding circuit operable in a fast scan and a slow scan conversion mode, said discrete differential coding circuit; (a) sampling the magnitude of said input FSTV signal at each of a plurality of fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode, the frequency of said fast scan sampling instant being equal to said fast scan sampling rate; and (b) sampling the magnitude of said input SSTV signal at each of a plurality of slow scan sampling instants when said discrete differential coding circuit is operated in said flow scan conversion mode, the frequency of said slow scan sampling instants being equal to said slow scan sampling rate; and (2) control means for selectively operating said discrete differential coding circuit and said fast scan or said slow scan conversion modes as selected; (E) said discrete differential coding circuit comprising; (1) feedback section means for; (a) generating a predicted FSTV signal representative of the predicted magnitude of said input FSTV signal at each successive fast scan sampling instant when said discrete differential coding circuit is operated in said fast scan conversion mode; and (b) generating a predicted SSTV signal representative of the predicted magnitude of said input SSTV signal at each successive slow scan sampling instant when said discrete differential coding circuit is operated in said slow scan conversion mode; and (2) encoding section means for; (a) generating a succession of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted FSTV signal and said input FSTV signal at respective ones of said fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode; and (b) generating a sequence of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted SSTV signal and said input SSTV signal at a respective one of said flow scan sampling instants when said discrete differential coding circuit is operated in said flow scan mode; (F) said feedback section means generating each said predicted FSTV and SSTV signal as a function of the last generated discrete differential coding circuit when operated at said fast scan and slow scan conversion modes, respectively; and (G) said feedback section means comprising; (1) decoder/weigher means responsive to said discrete differential coded signals for generating an output signal representative of the predicted change in magnitude between the last generated predicted FSTV and SSTV signals and the next generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively; (2) storage register means for storing the magnitude of the last generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan modes, respectively; and (3) adder means for adding said signal stored in said storage register means and said signal generated by said decoder/weigher means and for generating an output signal representative of the predicted FSTV and SSTV signals at the next fast scan and slow scan sampling instants when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively.
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Specification