Clock-controlled DC converter

• US 4,271,461 A
• Filed: 05/04/1979
• Issued: 06/02/1981
• Est. Priority Date: 05/16/1978
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Zapf, Karl, Hoffmann, Kurt
• Primary Examiner(s): Shoop, William M.
• Assistant Examiner(s): Wong, Peter S.
• Application Number:
  US06/036,070
• Time in Patent Office: 760 Days
• Field of Search: 363/59, 363/60, 363/61, 307/279, 307/296, 307/297, 307/303, 307/304, 307/109, 307/110, 357/41, 357/51
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A clock-controlled dc converter is provided in integrated semiconductor MOS technology and serves the supply voltage of integrated MOS circuits, particularly dynamic memories. The converter comprises a clock pulse generator having two outputs, supplying sequences of clock pulses which are inverted with respect to one another, which pulses are connected to the two clock pulse inputs of a first pulse level shifter. The first pulse level shifter comprises a bistable flip-flop lying at a supply potential, and which is switched as a level shifter. The two outputs of the first level shifter are connected, on the one hand, to the output of a voltage converter by way of the source-drain circuit of a respective field effect transistor. On the other hand, the two outputs are connected to the supply input of a respective pulse voltage doubler, which are in turn directly charged by a respective output of the clock pulse generator. The two pulse voltage doublers supply the clock pulse supply for a second pulse level shifter, likewise constructed as a bistable flip-flop, by way of the two outputs of which the connection between the outputs of the first level shifter and the output of the voltage comparator is controlled. The doubled supply voltage appears at the output of the voltage converter.

Claims

1. A clock-controlled d.c. converter, comprising:

a pair of clock pulse inputs each adapted to receive clock pulse trains which are inverted with respect to one another;

a first pulse level shifter including flip-flop comprising first, second, third and fourth field effect transistors each including a source, a drain and a control electrode,

said sources and drains of said first and second field effect transistors respectively connected together, and said sources and drains of said third and fourth field effect transistors respectively connected together,

said sources of said first and second field effect transistors and said sources of said third and fourth field effect transistors connected to respective ones of said pair of clock pulse inputs,

said drains and said control electrodes of said first, second, third and fourth transistors connected to a supply potential,

said sources of said first and second field effect transistors constituting a first output of said first pulse level shifter and said sources of said third and fourth field effect transistors constituting a second output of said first pulse level shifter, said first and second outputs carrying level shifted pulse trains which are inverted with respect to each other;

fifth and sixth field effect transistors each having a source-drain path connected to a respective output of said first pulse level shifter and connected to the source-drain path of the other constituting an output for said converter, and each having a control electrode,

first and second voltage doublers each including first and second inputs and an output, said first input of said first voltage doubler connected to receive the inverted clock pulses and said second input of said first voltage doubler connected to said first output of said first pulse level shifter, said first input of said second voltage doubler connected to receive non-inverted clock pulses and said second input connected to said second output of said first pulse level shifter, said voltage doublers operable to supply double voltage clock pulses at their outputs;

a second pulse level shifter including a bistable flip-flop having first and second inputs connected to respective outputs of said voltage doublers, and first and second outputs connected to respective control electrodes of said fifth and sixth field effect transistors.

2. The converter of claim 1, comprising:

first and second capacitors;

and wherein said bistable flip-flop of said second pulse level shifter comprises;

seventh and eigth field effect transistors each including a source, a control electrode cross-connected to said source of the other and a drain connected to the supply potential,

said clock pulse inputs coupled via respective ones of said first and second capacitors to respective control electrodes of said seventh and eighth field effect transistors, and

said sources of said seventh and eighth field effect transistors connected to said control electrodes of respective ones of said fifth and sixth field effect transistors.

3. The converter of claim 1, wherein each of said voltage doublers is a modified inverter which comprises:

a ninth field effect transistor including a control electrode and a drain together connected to a respective output of said first pulse level shifter, and a source;

a third capacitor connected to said source;

a tenth field effect transistor including a control electrode connected to said source of said ninth transistor and to said capacitor, a drain connected to said control electrode and drain of said ninth transistor, and a source connected via said third capacitor to said source of said ninth transistor; and

an eleventh field effect transistor including a drain connected to said source of said tenth transistor, a source connected to ground potential, and a control electrode connected to a respective clock pulse input,

the clock pulse outputs of said voltage doublers formed by the respective junctions between said tenth and eleventh transistors in each of said voltage doublers.

4. The converter of claim 3, comprising:

a pulse generator including first and second outputs connected to respective ones of said clock pulse inputs, said generator producing respective identical pulse trains at said outputs; and

an inverter interposed between one of said first and second outputs and the respective clock pulse input for inverting the respective pulse train.

5. The converter of claim 4, comprising:

a fourth capacitor connected as a filter between said output of said converter and ground.

6. The converter of claim 1, comprising:

a clock pulse generator connected to said first and second clock pulse inputs, said clock pulse generator including an oscillator including a pair of outputs, an inverter connected to one of said outputs, and an amplifier including a pair of inputs connected to the other output of said oscillator and to said inverter, respectively, and a pair of outputs connected to respective ones of said clock pulse inputs.

7. The converter of claim 6, wherein said amplifier comprises:

a bistable flip-flop including a pair of inputs connected to receive the inverted and non-inverted pulses, respectively, and including said pair of outputs of said amplifier.

8. The converter of claim 7, wherein said oscillator is an RC oscillator.

9. The converter of claim 7, wherein said pulse generator, said first and second pulse level shifters and said first and second voltage doublers are integrated together on the same integrated circuit chip.

10. The converter of claim 7, wherein said bistable flip-flop is a RS flip-flop and said amplifier further comprises:

said inverter as a first inverter, and second and third inverters, said second inverter connected between said first inverter and one of said flip-flop inputs as a first setting stage for said flip-flop, and said third inverter connected between said other output of said oscillator as a second setting stage for said flip-flop.

11. The converter of claim 10, comprising:

twelfth, thirteenth and fourteenth field effect transistors each including a control electrode, a drain and a source; and

a fifth capacitor connected, on the one hand, to said source of said twelfth transistor and said control electrode of said thirteenth transistor, and, on the other hand, to said source of said thirteenth transistor and said drain of said fourteenth transistor,

said control electrode and said drain of said twelfth transistor connected to the supply potential,

said drain of said thirteenth transistor connected to the supply potential and said source of said fourteenth transistor connected to a reference potential,

said fourteenth transistor forming part of said first inverter and said control electrode of said fourteenth transistor connected to said oscillator and to said third inverter to constitute both of said inputs of said amplifier.

12. The converter of claim 11, wherein said source of said fourteenth transistor is connected to ground as the reference potential.

13. The converter of claim 11, wherein each of said setting stages comprises:

fifteenth, sixteenth and seventeenth field effect transistors each including a drain, a source and a control electrode; and

a sixth capacitor,

said source of said fifteenth transistor connected to the reference potential,

said drain of said fifteenth transistor connected to said source of said sixteenth transistor and via said sixth capacitor to said control electrode of said sixteenth transistor and said source of said seventeeth transistor,

said control electrode and said drain of said seventeenth transistor connected to the supply voltage,

said drain of said sixteenth transistor connected to the supply voltage, and

said control electrodes of said fifteenth and sixteenth transistors connected to the respective output from the respective setting stage to the respective input of said bistable flip-flop of said amplifier.

14. The converter of claim 13, wherein said bistable flip-flop of said amplifier comprises:

eighteenth, nineteenth, twentieth, twenty-first, twenty-second, and twenty-third field effect transistors each including a drain, a source and a control electrode,

said drains of said eighteenth and twenty-first transistors connected to the supply voltage,

said control electrodes of said eighteenth and twenty-first transistors connected to respective ones of said setting stages,

said drains of said nineteenth and twentieth transistors connected to said source of said eighteenth transistor,

said drains of said twenty-second and twenty-third transistors connected to said source of said twenty-first transistor,

said control electrodes of said twentieth and twenty-second transistors cross-connected to said sources of each other,

said sources of said nineteenth, twentieth, twenty-second and twenty-third transistors connected to the reference potential, and

said control electrodes of said nineteenth and twenty-third transistors connected to said control electrodes of respective ones of said fifteenth transistors of said setting stages,

said drains of said nineteenth and twentieth transistors and of said twenty-second and twenty-third transistors constituting respective outputs of said amplifier.

15. The converter of claim 14, wherein:

said oscillator comprises a Schmitt trigger circuit, including a RC feedback coupling, connected between the supply voltage and ground.

16. The converter of claim 15, wherein said oscillator comprises:

a seventh capacitor; and

twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh and twenty-eighth field effect transistors each including a source, a drain and a control electrode,

said drain-source circuits of said twenty-fourth, twenty-fifth and twenty-sixth transistors connected in series between the supply voltage and the reference potential,

said control electrodes of said twenty-fourth and twenty-eighth transistors connected to the supply potential,

the drain-source path of said twenty-eighth transistor connected in series with said seventh capacitor between the junction of said twenty-fourth and twenty-fifth transistors and ground, with the junction of said twenty-eighth transistor and said seventh capacitor connected to said control electrodes of said twenty-fifth and twenty-sixth transistors,

said control electrode of said twenty-seventh transistor connected to the junction between said twenty-fourth and twenty-fifth transistors, which junction constitutes the output of said oscillator, and

the drain-source circuit of said twenty-seventy transistor connected between the supply potential and the junction of said twenty-fifth and twenty-sixth transistors.

17. The converter of claim 16, comprising:

an actual value generator connector to said output of said converter and responsive to the output signal to generate a corresponding actual value signal.

18. The converter of claim 17, comprising:

a reference value control loop connected between said output of said converter and said oscillator for providing a reference potential as a function of the output signal.

19. The converter of claim 18, wherein said control loop comprises:

a comparator including an output connected to said oscillator, an actual value input, and a reference value input;

twenty-ninth, thirthieth and thirty-first field effect transistors each including a drain, a source and a control electrode,

the drain-source circuits connected in series between said output of said converter and ground and each of said control electrodes connected to the respective drain so that the respective transistor operates as a resistor,

the junction of said twenty-ninth and thirtieth transistors connected to said actual value input and the junction of said thirthieth and thirty-first transistors connected to said reference value input.

20. The converter of claim 19, wherein said reference value generator comprises:

said thirty-first transistor; and

thirty-second and thirty-third field effect transistors each including a source, a drain and a control electrode,

the drain-source circuits of said thirty-second, thirty-third and thirty-first transistors connected in series between the supply voltage and ground, and

said control electrodes of said thirty-second and thirty-third transistors connected to the respective drains thereof with said drain and control electrode of said thirty-third transistor connected to said reference value input.

21. The converter of claim 20, wherein said comparator comprises:

thirty-fourth, thirty-fifth, thirty-sixth, thirty-seventh and thirty-eighth transistors each including a drain, a source and a control electrode,

a reference branch including the drain-source circuits of said thirty-fourth and thirty-fifth transistors connected in series with the drain-source circuit of said thirty-eighth transistor between the supply potential and ground, said control electrode of said thirty-fourth transistor connected to the supply voltage and said control electrode of said thirty-fifth transistor constituting said reference value input, and

an actual value branch including the drain-source circuits of said thirty-sixth and thirty-seventh transistors also connected in series with the drain-source circuit of said thirty-eighth transistor between the supply voltage and ground, said control electrode of said thirty-sixth transistor connected to the supply voltage and said control electrode of said thirty-seventh transistor constituting said actual value input,

a voltage divider connected between the supply voltage and ground, and

said control electrode of said thirty-eighth transistor connected to said voltage divider.

22. The converter of claim 21, comprising:

thirty-ninth, fourtieth and fourty-first transistors each including a drain, a source and a control electrode,

the drain-source circuits of said thirty-ninth and fourtieth transistors connected in series between the supply voltage and ground with the control electrodes connected to respective junctions of said thirty-fourth and thirty-fifth transistors and said thirty-sixth and thirty-seventh transistors,

the drain-source circuit of said fourty-first transistor connected between said source of said twenty-sixth transistor and ground,

said control electrode of said fourty-first transistor connected to the junction of said thirty-ninth and fourtieth transistors, and

said drain of said fourty-first transistor constituting a reference voltage output.

23. The converter of claim 22, wherein all of said field effect transistors are n-channel enhancement type transistors and said capacitors are metal-oxide semiconductor capacitors.

24. The converter of claim 22, wherein all of said field effect transistors are p-channel enhancement type transistors and said capacitors are metal-oxide semiconductor capacitors.

25. The converter of claim 1, comprising:

a pulse generator including an output connected to said clock pulse inputs, a plurality of inputs, and operable to provide timed output pulses in response pulses received at said inputs,

said pulse generator further comprising a plurality of monoflops each including a respective one of said pulse inputs and each connected to said output of said pulse generator.

26. The converter of claim 25, wherein each of said monoflops comprises:

seventh, eighth, ninth and tenth field effect transistors each including a source, a drain and a control electrode; and

a capacitor,

the drain-source circuits of said seventh and eighth transistors connected in series between the supply voltage and ground,

said control electrode of said seventh transistor connected to the supply voltage,

said control electrodes of said eighth and tenth transistors constituting the respective pulse input,

the drain-source circuits of said ninth and tenth transistors connected in series between said output and ground, and

the junction of said seventh and eighth transistors and said control electrode of said ninth transistor connected to ground via said capacitor.

27. The converter of claim 26, comprising:

an eleventh field effect transistor including a drain and a control electrode commonly connected to the supply voltage, and a source connected to said output.

28. A clock-controlled d.c. converter, comprising:

a clock-pulse generator including first and second clock outputs and operable to provide respective clock pulses which are inverted with respect to each other;

first and second pulse level shifters each including first and second inputs and first and second outputs;

said first and second inputs of said first pulse level shifter respectively connected to said first and second clock outputs;

said first pulse level shifter connected between a supply voltage and a reference potential;

a converter output for providing a voltage which is twice the supply voltage;

switching means operable to connect said first and second outputs of said first pulse level shifter with said converter output and including first and second control inputs respectively connected to said first and second outputs of said second pulse level shifter;

first and second voltage doublers connected between the supply voltage and the reference potential and each including first and second inputs and an output, each of said voltage doublers operable to provide clock pulses at twice the voltage of the voltage supply, said first inputs respectively connected to said second and first clock outputs, said second inputs respectively connected to said first and second outputs of said first pulse level shifter, and said outputs respectively connected to said first and second inputs of said second pulse level shifter.

29. The converter of claim 28, further comprising:

an additional converter output for providing an output voltage which is three-times the supply voltage;

third and fourth pulse level shifters each including first and second inputs and first and second outputs;

said third pulse level shifter connected to and operating at twice the supply voltage which appears at the first-mentioned output;

said first and second inputs of said third pulse level shifter respectively connected to said first and second clock outputs;

additional switching means operable to connect said first and second outputs of said third pulse level shifter to said additional converter output and including first and second control inputs respectively connected to said first and second outputs of said fourth pulse level shifter; and

third and fourth voltage doublers each including a first input respectively connected to said second and first clock outputs, a second input respectively connected to said first and second outputs of said third pulse level shifter, and an output respectively connected to said first and second inputs of said fourth pulse level shifter.

30. The converter of claim 28, further comprising:

an additional converter output for providing an output voltage which is four-times the supply voltage;

third and fourth pulse level shifters each including first and second inputs and first and second outputs;

said third pulse level shifter connected to and operating at twice the supply voltage which appears at the first-mentioned output;

said first and second inputs of said third pulse level shifter respectively connected to said outputs of said first and second voltage doublers;

additional switching means operable to connect said first and second outputs of said third pulse level shifter to said additional converter output and including first and second control inputs respectively connected to said first and second outputs of said fourth pulse level shifter; and

third and fourth voltage doublers each including a first input respectively connected to said outputs of said first and second voltage doublers, a second input respectively connected to said first and second outputs of said third pulse level shifter, and an output respectively connected to said first and second inputs of said fourth pulse level shifter.

31. A clock-controlled d.c. converter, comprising:

a clock-pulse generator including first and second clock inputs for receiving respective clock pulses which are inverted with respect to each other;

first and second pulse level shifters each including first and second inputs and first and second outputs;

said first and second inputs of said first pulse level shifter respectively connected to said first and second clock inputs;

said first pulse level shifter connected between a supply voltage and a reference potential;

a converter output for prodicing a voltage which is twice the supply voltage;

switching means operable to connect said first and second outputs of said first pulse level shifter with said converter output and including first and second control inputs respectively connected to said first and second outputs of said second pulse level shifter;

first and second voltage doublers connected between the supply voltage and the reference and each including first and second inputs and an output, each of said voltage doublers operable to provide clock pulses at twice the voltage of the voltage supply, said first inputs respectively connected to said second and first clock inputs, said second inputs respectively connected to said first and second outputs of said first pulse level shifter, and said outputs respectively connected to said first and second inputs of said second pulse level shifter.

32. The converter of claim 31, wherein:

said first and second pulse level shifters are constructed as field effect transistor flip-flops including n-channel enhancement type field effect transistors.

33. The converter of claim 31, wherein:

said first and second pulse level shifters are constructed as field effect transistor flip-flops including n-channel enhancement type field effect transistors.