High-speed acquisition system employing an analog memory matrix

• US 4,271,488 A
• Filed: 04/13/1979
• Issued: 06/02/1981
• Est. Priority Date: 04/13/1979
• Status: Expired due to Term

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Saxe, Charles L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/029,807
• Time in Patent Office: 781 Days
• Field of Search: 320/1, 365/45, 365/46, 365/48, 365/230
• US Class Current: 365/240
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A high-speed acquisition system employing an analog memory matrix is provided in which sample-hold elements connected to an analog bus are arranged in rows and columns to form an M×N matrix. The system is operable in a fast in-slow out mode, and the analog memory matrix may be implemented on a single integrated-circuit semiconductor chip.

Claims

1. A high-speed acquisition system, comprising:

analog signal input means and analog output means;

an analog bus coupled to said input means and said ouptput means;

a plurality of analog memory means disposed in M rows and N columns, said analog memory means being coupled to said analog bus; and

means for activating said analog memory means in a predetermined manner to provide store and readout operations, said means for activating said analog memory means comprising an X shift register having M outputs and a Y shift register having N outputs, M row control lines connected to the outputs of said X register, N column control lines connected to the outputs of said Y register, and means for operating said X shift register at at least one predetermined rate and for operating said Y shift register at a rate 1/M times the rate at which said X register is operated, wherein said row and column control lines form an M×

N matrix of electrical intersections each of which corresponds to an analog memory means, each of said analog memory means being connected to both a predetermined row control line and a predetermined column control line for activation thereby.

2. A high-speed acquisition system in accordance with claim 1 wherein said analog signal input means includes a first buffer amplifier and said output means includes a second buffer amplifier, wherein said input means further includes switch means interposed between the output of said first buffer amplifier and said analog bus for disconnecting said first buffer amplifier from said analog bus during said readout operation.

3. A high-speed acquisition system in accordance with claim 1 wherein said output means comprises a charge amplifier, said charge amplifier comprising an operational amplifier having an inverting input, a non-inverting input, and an output, capacitor connected between said output and said inverting input, and wherein the non-inverting input is grounded to provide a virtual ground at said inverting input to effectively eliminate stray capacitance of said analog bus.

4. A high-speed acquisition system in accordance with claim 3 wherein said capacitor has a switch connected thereacross to resist said capacitor by removing any charge stored therein.

5. A high-speed acquisition system in accordance with claim 1 wherein each of said analog memory means comprises a sample-hold element including a capacitive storage device connectable between ground and said analog bus through a dual-input switch means, said dual inputs corresponding respectively to a predetermined row and a predetermined column.

6. A high-speed acquisition system in accordance with claim 5 wherein said dual-input switch means comprises a pair of field-effect transistors serially disposed between said analog bus and said capacitive storage element, the gate of one of said field-effect transistors connected to a row control line and the gate of the other of said field-effect transistors connected to a column control line.

7. A high speed acquisition system in accordance with claim 1 wherein said operating means includes a clock circuit connected to the clock input of said X shift register.

8. A high-speed acquisition system in accordance with claim 1 wherein said M×

N matrix is split into an upper portion defined as m×

N and a lower portion defined as (M-m)×

N, and wherein said Y shift register includes an upper shift register for driving the column control lines of said upper portion and a lower shift register for driving the column control lines of said lower portion.