Inter-subsystem direct transfer system

• US 4,272,819 A
• Filed: 03/26/1979
• Issued: 06/09/1981
• Est. Priority Date: 03/31/1978
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tanaka, Hideo, Katsumata, Yutaka, Sanagi, Mitsuru
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/024,032
• Time in Patent Office: 806 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/22
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

In an inter-subsystem communication system which has a communication queue enqueued by one subsystem having processors and dequeued by another subsystem having processors, there is provided between the subsystems direct memory access means which permits either of the subsystems to directly access a memory of the other subsystem, and in a queue element enqueued by the one subsystem is inserted memory access control information necessary for accessing the one subsystem, whereby a high-grade function is performed by the plurality of subsystems. When the source subsystem issues an enqueue command, the queue element length of a queue element produced in response to the queue command is compared with a remaining space of the queue and, if the comparison result satisfies a predetermined condition, an overflow interruption is caused in the processor of the source subsystem, thereby to efficiently detect a queue overflow state or queue usable state.

Claims

1. An inter-subsystem direct transfer system for inter-subsystem communication between plural subsystems, said direct transfer system having a communication queue enqueued with queue elements by one of said subsystems selected as a source subsystem and dequeued by another one of said subsystems selected as a destination subsystem, each said subsystem having a respective processor and a respective memory, the processor of each said subsystem connected to the memory and to a respective part of said direct transfer system comprised in the same subsystem as the processor, said direct transfer system comprising

direct memory access means located at least in part in each said subsystem for permitting each said destination subsystem to directly access a memory of said source subsystem, and

means for each said source subsystem to insert into respective ones of said queue elements memory access information necessary for said direct accessing of the memory of said source subsystem by said destination subsystem.

2. The system of claim 1, said memory access information comprising a table address, a segment table length and a page size of a respective memory of the source subsystem and key information of a program status word, corresponding to information characterizing said source subsystem.

3. The system of claim 1 said destination subsystem comprising means for producing control information on the basis of said memory access information for said controlling of said direct accessing.

4. The system of claim 3,

said destination subsystem comprising means for transmitting a logic address as part of said control information, and

said direct memory access means comprising dynamic address translation means for translating said logic address according to said control informatin into an actual address for said direct accessing of the memory of the source subsystem.

5. The system of claim 4, said control information comprising mode designating information for controlling said dynamic address translation to cause said direct accessing to selectively use said logic address as an actual address.

6. The system of claim 4 or 5 comprising storage protection means, said storage protection means comprising,

means in said source subsystem for producing a storage key,

said memory access information for each said communication queue comprising key information of a program status word,

said control information comprising said key information of said program status word previously transmitted from said source subsystem, and

said dynamic address translation means comprising means for comparing said key information with said storage key.

7. An inter-subsystem direct transfer system for inter-subsystem communication of a source subsystem which enqueues a queue element in a queue of a predetermined capacity and a destination subsystem which dequeues the queue element from the queue to achieve said communication between subsystems, each said subsystem comprising a processor and a memory and means for issuing an enqueue command to generate a queue element of selected length said transfer system comprising

means for comparing the length of said queue element with the space remaining in said queue when said source subsystem issues said enqueue command and

means for selectively causing overflow interruption in said processor means of said source subsystem when the result of said comparing satisfies a predetermined condition.

8. The system of claim 7 comprising means for causing a queue usable interruption in said processor means of said source subsystem when the remaining space of said queue increases after the occurrence of said overflow interruption.

9. The system of claim 7 or 8, said processor of said source subsystem comprising means for generating an instruction to determine whether said queue is in said overflow state during the course of processing for said queue overflow interruption.

10. A system for communication between plural subsystems, each said subsystem comprising a processor and memory, said system comprising

a communication queue connected to each of said subsystems, said queue being enqueued by a first of said subsystems selected as a source subsystem and dequeued by a second one of said subsystems selected as a destination subsystem,

direct memory access means connected to each said subsystem for permitting said destination subsystem to directly access the memory in said source subsystem, and

means located in said source subsystem for generating direct access information and

means located in said destination subsystem for generating control information based at least in part on said direct access information for effecting said direct accessing of the memory of said source subsystem.