CCD memory retrieval system

• US 4,276,609 A
• Filed: 01/04/1979
• Issued: 06/30/1981
• Est. Priority Date: 01/04/1979
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Patel, Narendra M.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chan, Eddie P.
• Application Number:
  US06/001,034
• Time in Patent Office: 908 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/104
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing

Abstract

A data store and retrieval system is disclosed in which a pair of RAM buffer memories are coupled to a CCD page main memory to provide high-speed read/write access by a computer to the main memory. Each buffer memory has stored therein a page of data transferred from the CCD main memory. Compare means included in the system compares the page address requested by the computer with the page address stored in the buffer memories. If a comparison is found, the designated buffer memory is accessed for the requested data. Both read/write access is available under these conditions. If a no comparison is found, logic circuits located in the system using the requested page address transfer the page in which the requested address is located from the CCD main memory to the RAM buffer memories for access by the computer. If a write operation had occurred on a page stored in the buffer memories, the altered page is transferred back to the CCD main memory before a new page of data is transferred to the buffer memory other than the buffer memory in which the previous page address was found.

Claims

1. A memory system for use in a data processing system in which a central processor generates a sequence of requested read and write instructions including the address of the data to be accessed over a common bus, said system comprising:

a first operating main memory unit coupled to said common bus for storing data to be accessed by the central processor over said common bus;

a plurality of buffer memory units each having a higher operational speed than said first main memory unit and coupled to said main memory unit and the common bus for storing a portion of the data stored in said main memory unit;

an address register for each of said buffer memory units coupled to the common bus for storing the addresses of the data stored in an associated buffer memory unit;

comparison means for each of said buffer memory units coupled to the common bus and the address registers of an associated buffer memory unit for comparing the address of the requested data appearing on the common bus with the addresses stored in its coupled address register for outputting a first control signal upon finding a coincidence in one of said buffer memory units and a second control signal upon finding no coincidence in any of the buffer memory units;

a first bi-stable means coupled to the output of each of said comparision means, said common bus and said address registers for outputting a first memory enabling signal in response to the generation of said first control signal enabling the buffer memory unit in which the coincidence was found to be accessed by the address of the requested data appearing on the common bus, and enabling said address registers to store the address of the data written into said buffer memory units, said first bi-stable means being further operated in response to said second control signal and to the generation of the next sequential read and write instruction to output said first memory enabling signal to the buffer unit not previously accessed thereby enabling said buffer unit to receive the requested data from the main memory unit for storage therein;

and a second bi-stable means coupled to the output of each of said comparison means for outputting a third control signal in response to the generation of said second control signal, said system further including a third bi-stable means coupled to the output of said second bi-stable means for outputting a fourth control signal initiating the transfer of the requested data from the main memory unit to one of said buffer memory units in response to receiving said third control signal.

2. The memory system of claim 1 wherein said first operating main memory unit comprises a chargecoupled device memory and each of said buffer memory units comprises a dynamic random-access memory.

3. The memory system of claim 2 which further includes fourth bi-stable means coupled to the output of said first bi-stable means and said common bus, said fourth bi-stable means in response to receiving a write signal from the central processor over the common bus and said first memory enabling signal from said first bi-stable means outputs a fifth control signal indicating a write operation has occurred in the data stored in the buffer memory enabled by said first memory enabling signal.

4. The memory system of claim 3 which further includes:

first gate means coupled to the output of said fourth and first bi-stable means to output a sixth control signal upon receiving said first memory enabling signal and said fifth control signal, and

second gate means coupled to the output of said first gate means and said third bi-stable means to output a second memory enabling signal to said main memory unit in response to the generation of said fourth and sixth control signals whereby the main memory unit is enabled to receive the data stored in the buffer memory unit selected by said first enabling signal prior to the transfer of the requested data from the main memory unit to the selected buffer memory unit.

5. The memory system of claim 4 which further includes first counter means coupled to the output of said third bi-stable means and responsive to the generation of said fourth control signal for outputting a first count equal to the storage capacity of said main memory unit and a second count equal to the capacity of both the main memory unit and a buffer memory unit, said first counter means coupled to said third bi-stable means for disabling said third bi-stable means upon outputting said first count thereby disabling the transfer of data from the main memory unit to the buffer memory unit.

6. The memory system of claim 5 which further includes:

second counter means coupled to each of said buffer memory units for outputting a count comprising the address location of data transmitted to said buffer memory unit from main memory units;

and decoding means coupled to said common bus on which are present the address of the requested data and said second counter means, said decoder means coupled to the output of said third bi-stable means and adapted to select the output of said second counter means for transmission to one of said buffer memory units upon receiving said fourth control signals whereby the data transferred from said main memory unit to one of said buffer memory units is stored at an address generated by said second counter means.

7. The memory system of claim 6 which further includes adding means coupled to said second counter means and said decoding means for adding a count to the output of said second counter means when enabled, said adding means further coupled to the output of said first gate means and enabled upon the generation of said sixth control signal to output the address of the data stored in the buffer memory for transfer of the data to the main memory unit.