Clock circuitry for a data communication system

• US 4,276,651 A
• Filed: 01/29/1979
• Issued: 06/30/1981
• Est. Priority Date: 09/06/1977
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bench, Stephen M., Dirkes, William R., Juglekar, Manohar A., Secora, James C., Stephen, Michael A.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/007,087
• Time in Patent Office: 883 Days
• Field of Search: 178/69.1, 179/15 BS, 328/133, 328/134, 328/155, 325/418-423, 340/146.1 D, 340/146.1 AL, 364/111, 364/112, 375/81, 375/119, 375/120, 331/1 R, 331/1 A
• US Class Current: 375/376
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04W 56/001 Synchronization between nodes
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase

Abstract

A data communication system for use in the control and monitoring of mobile stations, for example, in a bus monitoring system, from a central station over a communication channel carrying both data and voice information. Information is encoded into digital messages having a start code followed by one or more data blocks. The start code identifies the beginning of the data block that follows and enables synchronization of clock circuitry to the received data frequency. The data blocks have N digital words with M binary bits where one word is a parity word and N-1 words are data words. Each of the data words has a data portion and parity portion coded for correction of at least one error. Reliability is enhanced by a data detector which discriminates between data and noise or voice to provide an indication of the presence of data. In transmitting the digital messages, the bits of the N words in each data block are interleaved to provide protection against error bursts.

Claims

1. A clock circuitry continuously synchronizable to a digital data signal serially transmitted by a data clock signal having a predetermined frequency, comprising:

delay means coupled to the digital data signal for providing a delayed digital data signal delayed with respect to the digital data signal by a predetermined time interval;

first combining means for combining the digital data signal and the delayed digital data signal to provide a bit-transition pulse signal for each bit transition of the digital data signal;

oscillator means for providing an oscillator clock signal having a free-running frequency substantially the same as the frequency of the data clock signal, said oscillator means further including Schmitt trigger gating means for providing the oscillator clock signal and buffer gating means capacitively coupled to the oscillator clock signal from the Schmitt trigger gating means for providing a clock-transition pulse signal for each predetermined logical state change of the oscillator clock signal; and

second combining means for combining the bit-transition pulse signals and clock-transition pulse signals to provide a phase correction signal and applying the phase correction signal to the Schmitt trigger gating means for synchronizing the phase of the oscillator clock signal to the phase of the data clock signal.

2. The clock circuitry according to claim 1, wherein the first combining means is an exclusive-OR gate.

3. The clock circuitry according to claim 2, wherein the second combining means includes first and second diodes each having cathode and anode terminals, the anode terminal of the first diode being connected to the bit-transition pulse signal from the exclusive-OR gate, the anode terminal of the second diode being connected to the clock-transition pulse signal from the buffer gating means, and the cathode terminals of the first and second diodes being commonly connected for providing the phase correction signal.