Power supply circuit for a data processor

• US 4,279,020 A
• Filed: 08/18/1978
• Issued: 07/14/1981
• Est. Priority Date: 08/18/1978
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Kutzavitch, Walter G., Christian, Ronald W.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US05/934,817
• Time in Patent Office: 1,061 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/226, 365/227, 365/228, 365/229
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3246 by software initiated power-off

Abstract

In order to extend battery life when batteries are used and to conserve energy when commercial power is used, it is highly desirable that power not be applied to a data processor when it is not operating. A power supply in accordance with the present invention includes a power-up and supply subcircuit (100) that applies power to an associated data processor (500) when a data input circuit (700) is operated to select a particular operation of the processor. When the processor completes its operation, it provides an output signal to a power-down subcircuit (200) of the power supply which then removes power from the processor.

Claims

1. A power supply circuit for a data processor to which a data input circuit is connected, operation of the data input circuit providing an input to the data processor, the power supply circuit including a power up circuit that is latched on responsive to the operation of the data input circuit and when latched on supplies power from a power source to the processor, the power up circuit comprising a single pair of complementary transistors arranged so that an output electrode of each transistor is connected to an input electrode of the other transistor, a first of the transistors having its third electrode adapted to be connected to the power source, and the second transistor having its third electrode connected to the power input of the data processor, the operation of the data input circuit completing a path from the input electrode of the first transistor to a point that is essentially at a common reference potential to latch the power up circuit on.

2. A power supply circuit as in claim 1 wherein the power up circuit comprises a pair of bipolar transistors, the collector of each transistor being connected to the base of the other transistor, a first of the transistors having its emitter adapted to be connected to the power source and its base connected to the data input circuit and the second transistor having its emitter connected to a point that is essentially at the common reference potential when the power up circuit is turned off, the emitter of the second transistor providing power for the processor when the power up circuit is turned on.

3. A power supply circuit as in claim 2 wherein the data input circuit comprises a keyboard operated switch array, the operation of any keyboard switch completing a conductive path from the base of the first transistor to a selected input port of the processor and through the processor to the point that is essentially at the common reference potential when the power up circuit is turned off.

4. A power supply circuit as in claim 3 wherein the path through the processor extends from the input port through an input protection diode connected to the input port and out a supply voltage port.

5. A power supply as in claim 2 further including a power down circuit comprising a third transistor having its collector-emitter path connected between the collector of the first transistor and the common reference potential, the base of the third transistor being connected to a port of the processor that provides an output indicating that the processor has completed its operation, the third transistor when turned on turning off the second transistor and thereby turning off the first transistor whereby power is removed from the processor.

6. A power supply circuit as in claim 2 further including a circuit for providing power to a volatile memory operating in conjunction with the processor, the memory power circuit comprising a series connected current limiting resistor and voltage reference zener diode adapted to be connected across the power source, and a third transistor having its base connected to the junction between the current limiting resistor and the diode and having its collector-emitter path connected between the other side of the resistor and a supply voltage port of the memory, the first transistor connecting a low resistance resistor in shunt with the current limiting resistor when the power up circuit is turned on.

7. A power supply circuit as in claim 6 further including a power down circuit comprising a fourth transistor having its collector-emitter path connected between the collector of the first transistor and the reference potential of the power source, the base of the fourth transistor being connected to a port of the processor that provides an output indicating that the processor has completed its operation, the fourth transistor when turned on, turning off the second transistor and thereby the first transistor whereby power is removed from the processor and the shunt resistor is removed from across the current limiting resistor to reduce the current provided to the memory.

11. A power supply circuit having a data processor and volatile memory, the power supply circuit including a subcircuit for supplying power to the memory, the memory supply subcircuit providing sufficient power to sustain the memory but not enough power to operate the memory when the processor is not in operation, and a subcircuit for supplying power to the processor, the processor supply subcircuit providing no power to the processor when the processor is not in operation, the processor supply subcircuit being responsive to an input to the processor for providing power to the processor and for increasing the power supplied by the memory supply subcircuit to a level sufficient to operate the memory.

8. A power supply circuit as in claim 11 wherein the memory supply subcircuit continuously provides a constant regulated voltage to the memory, the memory supply subcircuit providing just sufficient current to sustain the memory but not enough current to operate the memory when the processor supply subcircuit is in the standby state, the processor supply subcircuit when in the operate state increasing the current provided by the memory supply subcircuit to a level to enable operation of the memory.

9. A power supply circuit as in claim 8 wherein the memory supply subcircuit includes a current limiting element and voltage reference element connected in series and adapted to be connected across the power source, the memory supply subcircuit further including a transistor having its base connected to a junction between the current limiting element and the voltage reference element and having its collector-emitter path connected between the other side of the current limiting element and a supply voltage port of the memory.

10. A power supply circuit as in claim 9 wherein the processor supply subcircuit when in the operate state shunts the current limiting element of the memory supply subcircuit.

12. A power supply circuit as in claim 11 further including a power down subcircuit responsive to an output from the processor indicating the completion of its operation for causing the processor supply subcircuit to remove power from the processor and returning the memory supply subcircuit to providing just sufficient power to sustain the memory.