Block redundancy for memory array

• US 4,281,398 A
• Filed: 02/12/1980
• Issued: 07/28/1981
• Est. Priority Date: 02/12/1980
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: McKenny, Vernon G., Taylor, David L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/120,929
• Time in Patent Office: 532 Days
• Field of Search: 364/200, 365/189, 365/200, 365/210, 365/230, 365/239, 307/238, 307/279
• US Class Current: 365/200
• CPC Class Codes: G11C 29/80 with improved layout

Abstract

Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks on each side of a central row decoder. Each block includes an array of memory cells, column select, column decode, sense amp, data buffer and other overhead circuitry. One block of redundant circuitry is also provided for each set of four blocks and includes a redundant memory matrix, a redundant column decoder, a redundant column select, a redundant sense amp and a redundant data buffer. Incorporated within each primary memory block is a multiplex logic circuit which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer. Each multiplex logic circuit includes a polysilicon fuse which is permanently programmable from a closed to an open circuit condition by applying a high voltage to the external data bit terminal which corresponds with the defective memory block cells. According to this arrangement, for each group of blocks, one out of four primary memory arrays including the associated column select, column decoder, sense amp and data buffer, may be replaced during wafer testing and after encapsulation.

Claims

1. A fault tolerant memory system comprising:

a plurality of primary memory blocks having data storage cells arranged in rows and columns;

a redundant memory block of data storage cells arranged in rows and columns;

data detection means coupled to each primary and redundant memory block, said data detection means each including a data output node for separately conducting data from the storage cells of the block to which it is coupled to an external data terminal in response to row and column address signals;

a multiplexer circuit coupled to the data detection means for each primary memory block and to the corresponding external data terminal, each multiplexer circuit having primary and redundant data input nodes and a data output node, each primary data input node being coupled to the data output node of the corresponding data detection means, each redundant data input node being coupled to the data output node of the redundant memory block data detection means, and each multiplexer data output node being separately coupled to the corresponding external data terminal; and

,

independently programmable means for selectively rendering each multiplexer circuit from a first stable state to a second stable state, a first data path being established from the primary data node of the corresponding primary memory block to the corresponding external data terminal when the multiplexer citcuit is in its first stable state, and a second data path being established from the redundant data node of the redundant memory block to the corresponding external data terminal when the multiplexer is in its second stable state.

2. The fault tolerant memory system as defined in claim 1, each data detection means comprising a sense amp and a data buffer.

3. The fault tolerant memory system as defined in claim 1, said independently progrrammable means each comprising a repair buffer including a polycrystalline silicon fuse and a gate circuit coupled to said fuse for conducting heavy current flow through said fuse in response to a repair signal applied to the gate circuit and a programming voltage applied to the corresponding external data pin.

4. The fault tolerant memory system as defined in claim 1,

each multiplexer including first and second gate circuits connected in series electrical relation with the output data node of the corresponding primary memory block and redundant block, respectively, and each gate circuit having an output node connected in common for conducting data to the corresponding external data terminal;

and,

each independently programmable means including a fuse and a switching circuit coupled to said fuse, said switching circuit having first and second output nodes coupled to the first and second multiplexer gate circuits, respectively, the switching circuit developing enable and complement enable signals on the first and second output nodes, respectively, when said fuse is intact, and developing complement enable and enable signals on the first and second output nodes, respectively, when said fuse is in open circuit condition.

5. A fault tolerant memory system comprising, in combination:

a plurality of primary memory blocks each including multiple rows and columns of data storage cells;

a redundant memory block including multiple rows and columns of data storage cells;

cell selection means coupled to each primary and redundant memory block for simultaneously addressing a cell at identical row and column addresses in each block;

data detection means coupled to each cell selection means having an output data node separately conducting data to one of a plurality of external data terminals;

a multiplexer coupled to the data detection means of each primary memory block, each multiplexer having first and second control inputs, first and second data inputs, and a common data output, the first and second data inputs being connected to the data output node of the primary block data detection means and to the data output node of the redundant block data detection means, respectively, and the common data output being coupled to the corresponding primary block external data terminal; and

,

independently programmable means coupled to each multiplexer for logically enabling data transmission exclusively from the corresponding primary memory block or exclusively from the redundant memory block.

6. In a memory system of the type including a primary memory block having data storage cells arranged in rows and columns and cell selection/data detection circuitry for conducting data from the cells to an external data terminal, the improvement comprising:

a redundant memory block having data storage cells arranged in rows and columns and cell selection/data detection circuitry for conducting data from the cells of the redundant block;

a multiplexer interposed between the primary memory block, the redundant memory block and the external data pin for selectively enabling the transmission of data exclusively from the primary memory block or exclusively from the redundant memory block to the external data terminal; and

,

independently programmable means coupled to the multiplexer for controlling its operation, said programmable means being characterized by first and second programmable stable states, wherein data transmission from the primary memory block to the external data pin is enabled in response to the first stable state, and data transmission from the redundant memory block being enabled in response to the second stable state.