Multiple correlator reference processor

• US 4,283,767 A
• Filed: 05/03/1979
• Issued: 08/11/1981
• Est. Priority Date: 05/03/1979
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Rountree, Hoyt S.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US06/035,750
• Time in Patent Office: 831 Days
• Field of Search: 364/119, 364/820, 364/728, 364/517, 364/574, 343/5 PD, 343/5 SA, 367/120, 367/124, 367/125, 367/901, 340/554, 340/565
• US Class Current: 702/194
• CPC Class Codes: G01S 3/8006 Multi-channel systems specially adapted for direction-finding, i.e. having a single aerial system capable of giving simultaneous indications of the directions of different signals
• CPC Class Codes: G01S 3/807 the desired condition being maintained automatically
• CPC Class Codes: G01S 3/8083 determining direction of source
• CPC Class Codes: G01S 3/86 with means for eliminating undesired waves, e.g. disturbing noises
• CPC Class Codes: Y10S 367/901 Noise or unwanted signal reduction in nonseismic receiving system

Abstract

A signal processor for use with an array of antenna elements comprises a plurality of pairs of receiver channels which receive signals from respective halves of the array. The component of the signals resulting from noise, such as the noise generated within the ocean, is substantially decorrelated between the respective halves of the array, while a component of the signal obtained from a source of a desired signal is coherent between the two halves of the array. The signals in each pair of channels are translated to intermediate frequencies by mixing the signals with reference signals of differing frequencies in each of the respective pairs of channels. The translated signals in each pair of channels are then multiplied together to produce a signal of substantially constant amplitude which is suitable for detection, or for a bearing deviation indication. Output signals of the respective multipliers are summed together and passed through a low pass filter having a pass band approximately equal to the reciprocal of the anticipated dwell time of the signal source within the beam width of the array of antenna elements. The uncorrelated noise results in an alternating component in the products of the respective multipliers which are substantially cancelled in the summing and filtering to produce a higher signal-to-noise ratio.

Claims

1. A data processing system comprising:

a plurality of pairs of signal processing channels each channel of a pair being response to a different one of two input signals, each of said channels having mixing means for translating said input signal to an intermediate frequency, each of said channels producing output signals having the same waveform in the absence of noise;

means for generating a set of reference signals of different frequencies, individual ones of said reference signals being coupled to said mixing means in respective pairs of said channels to provide mixer output frequency signals having a frequency less than said input signals, the frequencies of respective ones of said reference signals being separated by an amount of frequency which is larger than the bandwidth of said input signals;

means for multiplying the output signal of the mixer of one channel of a pair with the output signal of the mixer in the other channel of said pair to provide a channel pair output signal; and

means for combining the channel pair output signals produced by the multiplying means of each pair of said signal processing channels to produce a combined signal wherein undulations induced by noise in the input signals each of said channels combine incoherently for a reduction in noise power while a component of said combined signal obtained from said input signals is coherently combined for increasing the ratio of signal power relative to noise power.

2. A system according to claim 2 wherein said multiplying means comprises an exclusive-OR circuit.

3. A system according to claim 2 wherein said multiplying means comprises a multiplier circuit preserving the linearity of the signals serving as factors in a multiplication operation of said multiplying circuit.

4. A system according to claim 3 further comprising a filter coupled to each said multiplying means for processing a product of said multiplying means, said filter being clocked at an undersampling rate.

5. A signal processor for obtaining data of a source of radiant energy impinging upon an array antenna comprising:

a pair of input terminals for coupling to different portions of an array antenna;

a plurality of signal processing channels each of which includes a pair of subchannels, each subchannel of a pair being coupled to respective ones of said input terminals, each of said subchannels having filtering means for delineating a pass band of signals incident upon said antenna;

a source of reference signals differing in frequency by an amount of frequency greater than the width of said pass band, individual ones of said reference signals being coupled to the pair of subchannels in respective ones of said channels;

each of said subchannels of a pair including means for mixing a different one of said reference signals with signals obtained from said input terminals;

each of said channels including means for correlating an output signal of one frequency from said mixing means in one of said subchannels with an output signal of the same one frequency from said mixing means in the other of said subchannels to provide a channel data signal;

wherein said

correlating means includes means for multiplying said signal in said one subchannel by said signal in said other subchannel, said multiplying means preserving the linearity of said signal in said first subchannel and said signal in said second subchannel; and

means for summing together the data signals of respective ones of said channels.

6. A processor according to claim 5 wherein said summing means includes a filter having a pass band smaller than the bandwidth of said subchannels.

7. A processor according to claim 5 comprising in addition an array antenna;

said input terminals being coupled to different portions of said array antenna.