Signal processor for digital echo canceller

• US 4,283,770 A
• Filed: 10/09/1979
• Issued: 08/11/1981
• Est. Priority Date: 10/09/1979
• Status: Expired due to Term

• Current Assignee: Tellabs Incorporated (Infinera Corp.)
• Original Assignee: Tellabs Incorporated (Infinera Corp.)
• Inventors: Stewart, Robert C.
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US06/082,710
• Time in Patent Office: 672 Days
• Field of Search: 364/724, 364/754, 364/757, 179/15.55 T, 179/170.2, 179/170.6, 179/175.31 E, 340/347 DD
• US Class Current: 708/625
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers

Abstract

A processor for an echo canceller generates an estimate of an actual echo on an echo path and applies the same to a subtractor circuit in the path to cancel the echo. To generate the echo estimate, the processor multiplies A-law digitally encoded samples of signals which cause the echo by A-law digitally encoded samples of impulse responses of the echo path and sums a plurality of the products. The particular manner of multiplying the A-law samples produces a product which is a precise linear representation of the product of the linear equivalents of the samples, and no errors or approximations occur in the multiplication or in generation of the echo estimate.

Claims

1. A system for multiplying first and second multibit factors quantized in conformity with a pseudo-logarithmic compression characteristic, wherein each factor has an exponent and a mantissa, comprising first circuit means for receiving the mantissas and for generating a data signal having a value in accordance with the sum and the product of the mantissas, said first circuit means also generating exponent carry signals as required by the values of the mantissas;

second circuit means for receiving the exponents and said carry signals and for generating a control signal having a value in accordance with the sum thereof; and

shifter circuit means for receiving said data and said control signals, said shifter circuit means having a plurality of outputs greater in number than the number of bits in said data signal and generating said data signal at individual ones of said outputs in accordance with the value of said control signal.

2. A system as in claim 1, each said shifter circuit output representing a separate binary bit position and said data signal having n bits, said shifter circuit generating said data signal at its first n outputs upon occurrence of a zero value of said control signal and shifting said data signal bits as a group along x of its outputs in response to a control signal value of x.

3. A system as in claim 1, wherein said system is for multiplying pluralities of pairs of first and second factors, including accumulator circuit means connected to receive said shifter circuit means output signals, said accumulator circuit means generating a summation of a plurality of output signals from said shifter circuit means.

4. A system as in claim 3, wherein the first and second factors each have a sign bit, including third circuit means for comparing the sign bits of the factors of each pair, said third circuit means being connected with said accumulator circuit to control the same to add or subtract each shifter circuit output signal from the summation therein in accordance with the sign bits being like or unlike, respectively.

5. A system for multiplying first and second A-law encoded binary factors, the first factor having an exponent x_e, a mantissa x_m and a sign bit and the second factor having an exponent h_e, a mantissa h_m and a sign bit, comprising first circuit means for receiving the mantissas at inputs thereto and for generating at outputs therefrom the quantities (x_m +1) and (h_m +1) and active carry bits x_c and h_c whenever the respective quantity equals zero, which occurs whenever the respective mantissa equals the maximum step value for the range of A-law encoding used;

multiplier circuit means for receiving said quantities and for multiplying the same to generate a product signal P_m ;

second circuit means for receiving said quantities and controllable to generate an output signal S_m which equals either zero, one of said quantities or a summation of both of said quantities;

a first adder circuit for generating at an output therefrom a summation Σ

_m of signals at inputs thereto, said first adder circuit receiving at its inputs said signals P.sub. m and S_m, and one of said adder circuit and said second circuit means providing 2⁴ weighting for said signal S_m in said summation signal Σ

_m ;

a second adder circuit for generating at an output therefrom a summation signal Σ

_e of signals at inputs thereto, said second adder circuit receiving at its inputs the exponents x_e and h_e ;

a decoder circuit for receiving the exponents x_e and h_e and said carry signals x_c and h_c, said decoder circuit having outputs which are selectively rendered active in accordance with the values of x_e, h_e, x_c and h_c, wherein two of said outputs E_c1 and E_c2 are applied to inputs to said second adder circuit, another two of said outputs x_i and h_i are applied to said second circuit means to control the same, and one output 2⁸ is applied to one of said second circuit means and said first adder circuit to cause the introduction, when said output is active, of 2⁸ into said signal Σ

_m ; and

shifter circuit means having data inputs for receiving said first adder circuit output signal Σ

_m and shift control inputs for receiving said second adder circuit output signal Σ

_e, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal Σ

_m and generating said signal Σ

_m at selected ones of said outputs in accordance with the value of said signal Σ

_e.

6. A system as in claim 5, wherein said system is for multiplying pluralities of pairs of first and second factors, including an accumulator circuit for receiving said shifter circuit means output signal, said accumulator circuit generating a summation of a plurality of output signals from said shifter circuit.

7. A system as in claim 6, including a comparator circuit for comparing the sign bits of each pair of factors and connected with said accumulator circuit to control the same to add or subtract the value of said shifter circuit output signal to or from the summation therein in accordance with the sign bits being like or unlike, respectively.

8. A system as in claim 5, wherein said decoder circuit outputs x_i, h_i and 2⁸ are active to control said second circuit means so that said signal S_m equals the sum of said quantities (x_m +1) and (h_m +1) and so that 2⁸ is introduced into said signal Σ

_m, and said decoder circuit outputs E_c1 and E_c2 are active to increment said signal Σ

_e in response to said carry bits x_c and h_c, respectively, being active, whenever neither of the exponents x_e and h_e equals zero.

9. A system as in claim 5, wherein said decoder circuit outputs E_c1 and x_i are active, said outputs h_i and 2⁸ are inactive, and said output E_c2 is active in response to said carry bit h_c being active, whenever the exponent x_e equals zero, the exponent h_e does not equal zero and the mantissa x_m is less than the maximum step value, so that said second circuit means is controlled so that said signal S_m equals said quantity (x_m +1), 2⁸ is not introduced into said signal Σ

_m and said signal Σ

_e is incremented by said decoder circuit output E_c1, as well as by said output E_c2 if said output is active.

10. A system as in claim 5, wherein said decoder circuit outputs E_c2 and h_i are active, said outputs x_i and 2⁸ are inactive, and said output E_c1 is active in response to said carry bit x_c being active, whenever the exponent h_e equals zero, the exponent x_e does not equal zero and the mantissa h_m is less than the maximum step value, so that said second circuit means is controlled so that said signal S_m equals said quantity (h_m +1), 2⁸ is not introduced into said signal Σ

_m and said signal Σ

_e is incremented by said decoder output E_c2, as well as by said output E_c1 if said output is active.

11. A system as in claim 5, wherein said decoder circuit outputs E_c1 and E_c2 are active and said outputs x_i, h_i and 2⁸ are inactive whenever both of the exponents x_e and h_e equal zero and each of the mantissas x_m and h_m is less than the maximum step value, so that said second circuit means is controlled so that said signal S_m equals zero, 2⁸ is not introduced into said signal Σ

_m and said signal Σ

_e is incremented by both of said decoder outputs E_c1 and E_c2.

12. A system as in claim 5, said second circuit means comprising first gate means having an input for receiving said quantity (x_m +1), an enable input for receiving said decoder means output x_i, and an output, second gate means having an input for receiving said quantity (h_m +1), an enable input for receiving said decoder means output h_i and an output, each said gate means generating at its output the signal at its input whenever the respective carry signal at its enable input is active, and a third binary adder circuit for receiving said gate means outputs and for generating at an output therefrom said signal S_m.

13. A system for multiplying first and second A-law encoded binary factors wherein the first factor has a non-zero exponent x_e, a mantissa x_m and a sign bit and the second factor has a non-zero exponent h_e, a mantissa h_m and a sign bit, comprising first circuit means for receiving the mantissas at inputs thereto and for generating at outputs therefrom the quantities (x_m +1) and (h_m +1) and active carry bits x_c and h_c whenever the respective quantity equals zero, which occurs whenever the respective mantissa equals the maximum step value for the range of A-law encoding used;

multiplier circuit means for receiving said quantities and for multiplying the same to generate a product signal P_m ;

a first binary adder circuit for receiving said quantities and for generating a summation signal S_m of the same;

a second binary adder circuit for generating at an output therefrom a summation signal Σ

_m of signals at inputs thereto, said second binary adder receiving said signals P_m and S_m at inputs thereto and one of said first and second binary adder circuits providing 2⁴ weighting for said signal S_m in said signal Σ

_m ;

means for applying a 2⁸ input signal to an input to one of said first and second binary adder circuits so that said signal Σ

_m equals (P_m +2⁴ S_m +2⁸);

a third binary adder circuit for receiving at inputs thereto the exponents x_e and h_e and signals representative of said carry bits x_c and h_c and for generating at an output therefrom a summation signal Σ

_e which equals the sum of the exponents plus one (+1) for each active carry bit; and

shifter circuit means having data inputs for receiving said signal Σ

_m and shift control inputs for receiving said signal Σ

_e, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal Σ

_m and generating said signal Σ

_m at selected ones of its outputs in accordance with the value of said signal Σ

_e.

14. A system as in claim 13, wherein said system is for multiplying pluralities of pairs of first and second factors, including an accumulator circuit for receiving said shifter circuit means output signals and for generating a summation of a plurality of said signals, and a comparator circuit for comparing the sign bits of each pair of factors and connected with said accumulator circuit for controlling the same to add or subtract the value of said shifter circuit output signal to or from the summation therein in accordance with the sign bits being like or unlike, respectively.

15. A system for multiplying first and second A-law encoded binary factors wherein the first factor has an exponent x_e equal to zero, a mantissa x_m having a value less than the maximum step value for the range of A-law encoding used and a sign bit, and the second factor has a non-zero exponent h_e, a mantissa h_m and a sign bit, comprising first circuit means for receiving the mantissa at inputs thereto and for generating at outputs therefrom the quantities (x_m +1) and (h_m +1) and an active carry bit h_c whenever the quantity (h_m +1) equals zero, which occurs whenever the mantissa h_m has the maximum step value;

multiplier circuit means for receiving said quantities and for multiplying the same to generate a product signal P_m ;

a first binary adder circuit for receiving at inputs thereto said quantity (x_m +1) and said signal P_m, said binary adder circuit providing 2⁴ weighting for said quantity (x_m +1) and generating at an output therefrom a summation signal Σ

_m equal to [P_m +2⁴ (x_m +1)];

second circuit means for receiving the exponent h_e and said carry bit h_c at inputs thereto and for generating an output signal Σ

_e equal to (h_e +1) if the carry bit h_c is inactive or (h_e +2) if the carry bit h_c is active; and

shifter circuit means having data inputs for receiving said signal Σ

_m and shift control inputs for receiving said signal Σ

_e, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal Σ

_m and generating said signal Σ

_m at selected ones of its outputs in accordance with the value of said signal Σ

_e.

16. A system as in claim 15, wherein said system is for multiplying pluralities of pairs of first and second factors, including an accumulator circuit for receiving said shifter circuit means output signals and for generating a summation of a plurality of said signals, and a comparator circuit for comparing the sign bits of each pair of factors and connected with said accumulator circuit for controlling the same to add or subtract the value of each said shifter circuit output signal to or from the summation therein in accordance with the sign bits being like or unlike, respectively.

17. A system for multiplying first and second A-law encoded binary factors wherein the factors have exponents equal to zero, respective mantissas x_m and h_m each having a value less than the maximum step value for the range of A-law encoding used and sign bits, comprising first circuit means for receiving the mantissas x_m and h_m, for generating the quantities (x_m +1) and (h_m +1), and for multiplying said quantities to generate a product signal P_m ;

shifter circuit means having data inputs for receiving said signal P_m and a shift control input, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal P_m and generating said signal P_m at selected ones of its outputs as determined by the value of the signal at its shift control input; and

means for applying a signal to said shift control inputs to operate said shifter circuit to shift said signal P_m two places along its outputs.

18. A system as in claim 17, wherein said system is for multiplying pluralities of pairs of first and second factors, including an accumulator circuit for receiving said shifter circuit means output signals and for generating at an output therefrom a summation of a plurality of said signals, and a comparator circuit for comparing the sign bits of each pair of factors and connected with said accumulator circuit for controlling the same to add or subtract the value of each said shifter circuit output signal to or from the summation therein in accordance with the sign bits being like or unlike, respectively.

19. A method of multiplying first and second multibit factors quantized in conformity with a pseudologarithmic compression characteristic, wherein one factor represents a signal that causes an echo on an echo path of a transmission system and the other the impulse response of the system, in order to generate an echo estimate for subtraction from the echo on the echo path, and wherein each factor has an exponent and a mantissa, comprising the steps of summing signals representative of the sum and of the product of the mantissas to generate a data signal;

generating exponent carry signals as required by the values of the mantissas;

summing the exponents and said carry signals to generate a control signal; and

shifting said data signal by a number of bit places equal to the value of said control signal to generate the product of the factor.

20. A method as in claim 19, wherein pluralities of pairs of factors are multiplied, including the step of summing a plurality of products of the factors.

21. A method as in claim 20, wherein the first and second factors each have a sign bit, including the steps of comparing the sign bits of the factors of each pair, and controlling the step of summing a plurality of factor products to add or subtract each product to or from the summation in accordance with the sign bits being like or unlike, respectively.

22. A method as in claim 21, including the step of subtracting the summation of the plurality of factor products from the echo signal on the echo path.

23. A method of multiplying first and second A-law encoded binary factors, wherein one factor represents a signal that causes an echo on an echo path for a transmission system and the other the impulse response of the system, in order to generate an echo estimate for subtraction from the echo on the echo path, and wherein the first factor has a non-zero exponent x_e, a mantissa x_m and a sign bit and the second factor a non-zero exponent h_e, a mantissa h_m and a sign bit, comprising the steps of incrementing each of the mantissas to generate the quantities (x_m +1) and (h_m +1);

generating a carry bit x_c and h_c whenever a respective quantity (x_m +1) and (h_m +1) equals zero, which occurs whenever the respective mantissa equals the maximum step value for the range of A-law encoding used;

multiplying said quantities to generate a product P_m thereof;

adding said quantities to generate a summation S_m of the same;

weighting said summation S_m by 2⁴ to generate 2⁴ S_m ;

adding said weighted summation 2⁴ S_m and said product P_m to generate a summation Σ

_m thereof;

incrementing said summation Σ

_m by 2⁸ so that the same equals (P_m +2⁴ S_m +2⁸);

adding the exponents and incrementing the same by plus one (+1) for each generated carry bit x_c and h_c to generate a summation Σ

_e ; and

shifting said summation Σ

_m by a number of bit places equal to the value of said summation Σ

_e to generate the product of the factors.

24. A method as in claim 23, wherein pluralities of pairs of factors are multiplied, including the steps of summing a plurality of products of the factors, comparing the sign bits of the factors of each pair, and controlling the step of summing a plurality of the factor products in order to add or subtract each product to or from the summation in accordance with the sign bits being like or unlike, respectively.

25. A method as in claim 24, including the step of subtracting the summation of the plurality of factor products from the echo signal on the echo path.

26. A method of multiplying first and second A-law encoded binary factors, wherein one factor represents a signal that causes an echo on an echo path of a transmission system and the other the impulse response of the system, in order to generate an echo estimate for subtraction from the echo on the echo path, and wherein the first factor has an exponent x_e which equals zero, a mantissa x_m having a value less than the maximum step value for the range of A-law encoding used and a sign bit, and the second factor has a non-zero exponent h_e, a mantissa h_m and a sign bit, comprising the steps of incrementing each of the mantissas to generate the quantities (x_m +1) and (h_m +1);

generating a carry bit h_c whenever the mantissa h_m has the maximum step value;

multiplying said quantities to generate a product P_m thereof;

weighting said quantity (x_m +1) by 2⁴ to generate 2⁴ (x_m +1);

adding said weighted quantity 2⁴ (x.sub. m +1) and said product P_m to generate a summation Σ

_m thereof;

generating an output signal Σ

_e which equals (h_e +1) if said carry bit h_c is inactive or (h_e +2) if said carry bit h_c is active; and

shifting said summation Σ

_m by a number of bit places equal to the value of said summation Σ

_e to generate the product of the factors.

27. A method as in claim 26, wherein pluralities of pairs of factors are multiplied, including the steps of summing a plurality of products of the factors, comparing the sign bits of the factors of each pair, and controlling the step of summing a plurality of the factor products in order to add or subtract each product to or from the summation in accordance with the sign bits being like or unlike, respectively.

28. A method as in claim 27, including the step of subtracting the summation of the plurality of factor products from the echo signal on the echo path.

29. A method of multiplying first and second A-law encoded binary factors, wherein one factor represents a signal that causes an echo on an echo path of a transmission system and the other the impulse response of the system, in order to generate an echo estimate for subtraction from the echo on the echo path, and wherein the factors have exponents equal to zero, respective mantissas x_m and h_m each having a value less than the maximum step value for the range of A-law encoding used and sign bits, comprising the steps of incrementing each of the mantissas to generate the quantities (x_m +1) and (h_m +1);

multiplying said quantities to generate a product P_m thereof; and

shifting said product P_m by two bit places to generate the product of the factors.

30. A method as in claim 29, wherein pluralities of pairs of factors are multiplied, including the steps of summing a plurality of products of the factors, comparing the sign bits of the factors of each pair, and controlling the step of summing a plurality of the factor products in order to add or subtract each product to or from the summation in accordance with the sign bits being like or unlike, respectively.

31. A method as in claim 30, including the step of subtracting the summation of the plurality of factor products from the echo signal on the echo path.

32. A system for multiplying first and second multibit factors quantized in confirmity with a pseudologarithmic compression characteristic, wherein each factor has an exponent and a mantissa, comprising first circuit means for receiving the mantissas and for generating a data signal having a value in accordance with a summation of (a) the sum of the mantissas and (b) the product of the mantissas, said first circuit means also generating exponent carry signals as required by the values of the mantissas;

second circuit means for receiving the exponents and the carry signals and for generating a control signal having a value in accordance with the sum thereof; and

shifter circuit means for receiving said data and said control signals, said shifter circuit means having a plurality of outputs greater in number than the number of bits in said data signal and generating said data signal at individual ones of said outputs in accordance with the value of said control signal.

33. A system as in claim 32, wherein said first factor has an exponent x_e and a mantissa x_m, said second factor has an exponent h_e and a mantissa h_m, and wherein said data signal generated by said first circuit means comprises the summation of (a) the sum of (x_m +1) and (h_m +1) and (b) the product of (x_m +1) and (h_m +1).

34. A system as in claim 33, wherein a first carry signal is generated whenever (x_m +1), and a second carry signal is generated whenever (h_m +1), equal the maximum step value for the range of pseudo-logarithmic quantizing used.

35. A method of multiplying first and second multibit factors quantized in conformity with a pseudo-logarithmic compression characteristic, wherein one factor represents a signal that causes an echo on a echo path of a transmission system and the other the impulse response of the system, to generate an echo estimate for subtraction from the echo on the echo path, and wherein each factor has an exponent and a mantissa, comprising the steps of summing signals respresentative of (a) the sum of the mantissas and (b) the product of the mantissas to generate a data signal, generating exponent carry signals as required by the values of the mantissas;

summing the exponents and said carry signals to generate a control signal; and

shifting said data signal by a number of bit places equal to the value of said control signal to generate the product of the factors.

36. A method as in claim 35, wherein said first factor has an exponent x_e and a mantissa x_m and said second factor has an exponent h_e and a mantissa h_m, and wherein said step of generating said data signal comprises generating the summation of (a) the sum of (x_m +1) and (h_m +1) and (b) the product of (x_m +1) and (h_m +1).

37. A method as in claim 36, wherein said step of generating exponent carry signals comprises generating a first carry signal whenever (x_m +1), and a second carry signal whenever (h_m +1), equal the maximum step value for the range of pseudo-logarithmic quantizing used.