Memory circuit
First Claim
1. A memory circuit comprisinga memory cell including two complementary transistors operatively connected to form a four-layer semiconductor having an input for receiving a data signal to be stored therein,a control input circuit including transistor means having at least one input transistor with its collector connected to the input of said memory cell,first input means connected to said control input circuit including first, econd and third input terminals receiving respective logical signals,second input means including a fourth input terminal receiving a data signal to be stored in said memory cell, means for connecting said fourth input terminal to an emitter of said input transistor andsaid control input circuit further including control means for controlling the base current of said input transistor on the basis of a logical product of the signals applied to said first, second and third input terminals.
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Accused Products
Abstract
A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.
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Citations
11 Claims
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1. A memory circuit comprising
a memory cell including two complementary transistors operatively connected to form a four-layer semiconductor having an input for receiving a data signal to be stored therein, a control input circuit including transistor means having at least one input transistor with its collector connected to the input of said memory cell, first input means connected to said control input circuit including first, econd and third input terminals receiving respective logical signals, second input means including a fourth input terminal receiving a data signal to be stored in said memory cell, means for connecting said fourth input terminal to an emitter of said input transistor and said control input circuit further including control means for controlling the base current of said input transistor on the basis of a logical product of the signals applied to said first, second and third input terminals.
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6. A memory circuit as claimed in claim 12, wherein said control means is constituted of at least first and second diodes, and said input transistor has its base connected through an impedance element with said first input terminal and its emitter connected through third and fourth diodes connected in inverse parallel configuration with each other to said fourth input terminal, said first and second diodes having their cathodes connected respectively to said second and third input terminals and their anodes connected in common with said base of said input transistor.
Specification