Four terminal voltage tripler for monolithic LCD clock circuit

• US 4,290,100 A
• Filed: 03/24/1980
• Issued: 09/15/1981
• Est. Priority Date: 03/24/1980
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Squires, David R.
• Primary Examiner(s): BEHA JR, WILLIAM
• Application Number:
  US06/132,819
• Time in Patent Office: 540 Days
• Field of Search: 363/59, 363/60, 363/147, 307/110, 340/811, 368/203, 368/204
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A voltage tripler for multiplying a DC voltage from a battery to provide a driving voltage for an LCD display in a digital clock. The circuit includes a charging capacitor and two storage capacitors and a plurality of switches for interconnecting the capacitors with the battery. The switches are controlled by means of driving circuitry which provides break-before-make type switching. The operation of the circuit is divided into four phases. During an initial phase the charging capacitor is charged to the voltage of the battery. During the second phase the charging capacitor is connected in parallel with one of the storage capacitors in order to transfer a portion of the charge to the storage capacitor. During the third phase the charging capacitor is again connected to the battery to recharge the charging capacitor. During the fourth phase, the charging capacitor is connected in parallel with the other storage capacitor so as to transfer charge to the storage capacitor. By repeating the sequence a plurality of times, the voltage on each of the storage capacitors will approach that of the battery. By referencing one of the capacitors to the negative terminal of the battery, the voltage at the free terminal of the other capacitor will be three times the battery voltage. This circuit is implemented on a monolithic integrated circuit and requires four terminals instead of five as in the prior art, thereby decreasing pin count and saving significant chip area.

Claims

1. A circuit for tripling the voltage of a D.C. voltage supply comprising:

a first capacitor;

a second capacitor having a first terminal connected to a first voltage supply;

a third capacitor connected in series with the second capacitor, the third capacitor including a first terminal connected to the second capacitor and an output terminal; and

a plurality of switches for sequentially connecting the voltage supply and the capacitors in the following configurations;

(a) a first phase during which the first capacitor is connected across the voltage supply to thereby charge the first capacitor,

(b) a second phase during which the first capacitor is connected in parallel with the second capacitor,

(c) a third phase during which the first capacitor is again connected across the voltage supply, and

(d) a fourth phase during which the first capacitor is connected in parallel with the second capacitor, whereby by repeating said four phases a plurality of times, the voltage at the output terminal referenced to a second terminal of the voltage supply will approach three times the supply voltage.

2. The voltage tripler of claim 1 wherein said switches are FET switches.

3. The voltage tripler of claim 1 wherein said voltage supply has a nominal value of 1.5 volts.

4. The voltage tripler of claim 2 including timing means for breaking switch connections at the end of one phase prior to making switch connections at the beginning of a subsequent phase.

5. A circuit for multiplying the voltage of a DC supply voltage having first and second terminals comprising:

a charging capacitor;

a first storage capacitor having a first terminal connected to the first terminal of the voltage supply;

a second storage capacitor having a first terminal connected to the second terminal of the first storage capacitor, the second terminal of the second storage capacitor comprising an output of said circuit;

a plurality of switches for selectively interconnecting the capacitors and the voltage supply; and

clock controlled driving circuitry for sequentially operating the switches so as to;

(a) charge the charging capacitor across the voltage supply,

(b) transfer a portion of the charge on the charging capacitor to the first storage capacitor,

(c) again charge the charging capacitor across the voltage supply,

(d) transfer a portion of the charge on the charging capacitor to the second storage capacitor, and

(e) repeat steps (a) through (d), whereby the voltage of the output terminal referenced to the second terminal of the voltage supply will asymptotically increase to a value which is a predetermined multiple of the supply voltage.

6. The circuit of claim 5 wherein said switches are FET switches.

7. The circuit of claim 6 wherein said switches and driving circuitry are contained on a monolithic chip.

8. The circuit of claim 6 wherein the driving circuitry includes delay circuitry for opening the switches at the end of a sequential step prior to closing selected switches to perform the next sequential step, thereby preventing charge leakage in the circuit.

9. The circuit of claim 5 wherein the output terminal is connected to a liquid crystal display through a logic circuit.

10. The circuit of claim 5 wherein the DC supply voltage is a battery.

11. The circuit of claim 10 wherein the first storage capacitor is connected to the negative terminal of the battery and wherein the switches include:

first and second switches for connecting the negative terminal of the battery with both terminals of the charging capacitor;

a third switch for connecting a first terminal of the charging capacitor with the positive terminal of the battery;

a fourth switch for connecting a second terminal of the charging capacitor with the second terminal of the first storage capacitor;

a fifth switch for connecting the first terminal of the charging capacitor with the first terminal of the second storage capacitor; and

a sixth switch for connecting the second terminal of the charging capacitor with the second terminal of the second storage capacitor.

12. The circuit of claim 8 wherein said delay circuitry includes:

a first level shifter having an input of a first clock frequency and a pair of out of phase outputs of substantially the same frequency as the first clock frequency, wherein the rising edges of said outputs are steeper than their falling edges;

a second level shifter having an input of a second clock frequency and a pair of out of phase outputs of substantially the same frequency as said second clock frequency, wherein the rising edges of said outputs are steeper than their falling edges; and

logic circuitry connected between the outputs of the level shifters and the switches.