Circuit arrangement for monitoring the state of signal systems, particularly traffic light signal systems
First Claim
1. A circuit arrangement for monitoring the state of a signal system, comprising:
- a memory means storing a plurality of test signals corresponding to inadmissible signal states;
an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state; and
signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to equality of an actual state signal and a test signal.
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Accused Products
Abstract
A circuit arrangement for monitoring the state of signal systems, particularly traffic light systems monitors different signal states as to the admissability or inadmissibility thereof in a simple manner without the necessity of carrying out manual wiring manipulations given a change of the signal conditions in adaptation to changed conditions or given an expansion of the signal system to be monitored. For this purpose, test signals which indicate test signal states are fixed in a memory and are processed with the signals indicating the respectively existing actual signal state of the signal transmitters in at least one microprocessor in such a manner that each signal indicating an actual state is compared with all test signals which are called up step-by-step in succession from the memory.
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Citations
15 Claims
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1. A circuit arrangement for monitoring the state of a signal system, comprising:
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a memory means storing a plurality of test signals corresponding to inadmissible signal states; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to equality of an actual state signal and a test signal. - View Dependent Claims (2)
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3. A circuit arrangement for monitoring the state of a signal system, comprising:
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a memory means storing a plurality of test signals corresponding to admissible actual states; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to inequality of an actual state signal and a test signal. - View Dependent Claims (4)
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5. A circuit arrangement for monitoring the state of a signal system, comprising:
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a memory means storing a plurality of test signals indicating test signal states, said memory means comprising first and second memories each storing a respective group of said test signals; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state, said evaluation means comprising first and second evaluation devices each including an input for receiving the predetermined clock pulse sequence and an output for indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual state signal with all test signals and emit said predetermined clock pulse sequence in response to a comparison indicating an inadmissible actual state, said signal comparison means comprising first and second microprocessors connected to receive respective groups of actual state signals from said first inputs and connected to respective ones of said memories for receiving respective groups of test signals, and first and second program means connected to respective microprocessors for programming said microprocessors to compare the actual and test signals, each of said microprocessors connected to the input of a respective evaluation device. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification