Audio signal recognition computer

• US 4,292,470 A
• Filed: 09/10/1979
• Issued: 09/29/1981
• Est. Priority Date: 09/10/1979
• Status: Expired due to Term

• Current Assignee: GTE Mobile Communications Service Corporation (Verizon Communications Inc.)
• Original Assignee: Interstate Electronics Corp. (L3Harris Technologies, Inc.)
• Inventors: An, Byung H.
• Primary Examiner(s): Nussbaum, Mark E.
• Assistant Examiner(s): Kemeny, E. S.
• Application Number:
  US06/073,792
• Time in Patent Office: 750 Days
• Field of Search: 179/1.5 D, 179/1.5 B, 179/1.5 C, 179/15.55 R, 340/146.3 H, 340/146.3 MA, 364/200, 364/900
• US Class Current: 704/253
• CPC Class Codes: G10L 15/285 Memory allocation or algorithm optimisation to reduce hardware requirements
• CPC Class Codes: G10L 25/87 Detection of discrete points within a voice signal

Abstract

A signal encoder and classifier particularly adapted to speech recognition includes a circularly addressed buffer which is independently addressed by a new data writing address system and a buffered data reading system so that writing and reading of data may be accomplished on a time shared basis. This time shared operation permits serial writing and reading of the pattern data without interrupting income signal storage. The writing data address system addresses the data into the buffer in a circular fashion while the reading data address system utilizes stored addresses identifying the beginning and end of the signal patterns for addressing sequential patterns from the buffer.

Claims

1. A signal pattern encoder including a transducer, a signal processing assembly coupled to the output of said transducer for providing spectrum samples representative of the signal output of said transducer and a timing and control assembly connected to said signal processing assembly wherein the improvement comprises:

event encoding logic means coupled to the output of said signal processing assembly and also coupled to said timing and control assembly for computing the difference between a current spectrum sample and the last previous spectrum sample accepted by said event encoding logic means;

first means responsive to said event encoding logic means for rejecting said current spectrum sample if said difference is below a predetermined value;

second means responsive to said event encoding logic means for encoding said current spectrum sample into a binary signal if said difference is above said predetermined value;

circularly addressed data buffer means connected to said encoding means for continuously storing said encoded spectrum samples within said circularly addressed data buffer means;

an event detector connected to said circularly addressed data buffer means and responsive to said event encoding logic means for determining the boundaries of a particular event, and for storing the addresses within said circularly addressed data buffer means of said boundaries; and

third means connected to said circularly addressed data buffer means and responsive to said event detector for reading data relating to said particular even from said circularly addressed data buffer means.

2. A signal pattern encoder, as defined in claim 1, additionally comprising:

means for time sharing the interface between said second means, said third means and said circularly addressed data buffer means to permit said second means and said third means to write and read, respectively, data in different locations of said circularly addressed data buffer means on a time shared basis.

3. A signal pattern encoder as defined in claim 1 wherein said event detector is responsive to the beginning and end of signal patterns provided by said transducer.

4. A signal pattern encoder, as defined in claim 3, wherein said event detector further comprises:

means for counting sequential outputs of said event encoding logic means relating to current spectrum samples wherein said difference is above said predetermined value; and

means responsive to said counting means for determining the beginning of said particular event when said counting means reaches a predetermined count.

5. A signal pattern encoder, as defined in claim 3, wherein said event detector further comprises:

a counter responsive to said event encoding logic means for counting sequential current spectrum samples wherein said difference is below said predetermined value; and

means responsive to said counting means for determining the end of said particular event when said counter reaches a second predetermined value.

6. A signal pattern encoder, as defined in claim 1, wherein said circularly addressed data buffer means provides sufficient storage for storing each of said encoded spectrum samples of the longest expected signal pattern provided by said transducer.

7. A signal pattern encoder, as defined in claim 1, wherein said event detector comprises:

first register means for storing the address of the beginning of data in said circularly addressed data buffer means relating to said specific event; and

second register means for storing the address of the end of data in said circularly addressed data buffer means relating to said specific event.

8. A signal pattern encoder, as defined in claim 7, additionally comprising:

third register means connected to said first register means for storing the address of beginning of data in said circularly addressed data buffer means relating to additional specific events; and

fourth register means connected to said second register means for storing the address of the end of data in said circularly addressed data buffer means relating to said additional specific events.

9. A signal pattern encoder, as defined in claim 1, further comprising:

means for storing the address of the last location of said circularly addressed data buffer means;

means for identifying the address of the location of said circularly addressed data buffer means currently storing said encoded spectrum samples from said second means;

means for comparing the data in said address storing means with the data in said address identifying means; and

means responsive to said comparing means for entering binary data from said second means into the first location of said circularly addressed data buffer means.