Reconfigurable key-in-storage means for protecting interleaved main storage

• US 4,293,910 A
• Filed: 07/02/1979
• Issued: 10/06/1981
• Est. Priority Date: 07/02/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tan, Kwang G., Flusche, Frederick O., Wright, Ralph W.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chan, Eddie P.
• Application Number:
  US06/054,350
• Time in Patent Office: 827 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/157
• CPC Class Codes: G06F 12/1466 Key-lock mechanism

Abstract

The disclosure provides a storage protection (SP) array in each of two system controllers (SCs) in a multiprocessing system which has a shared main storage containing a plurality of basic storage modules (BSMs). The BSMs may be operated with block and page interleaved addresses. Each block in main storage is assigned a key-in-storage having an entry in one of the two arrays.

A cross-interrogate (XI) bus connects between the SCs. Using the XI bus, each processor request is sent to an SP address register in every SP array.

Each array is divided into a plurality of equal groups. Each group has a range identifier register and a comparator. The range identifier register is loaded with a value which controls the range of main storage addresses to which the group is assigned. All of the comparators in each array are connected to a high-order part of the SP address register for the array.

The range identifier registers in all of the groups in both arrays are assigned different values which cover the entire address range of main storage, and only one array need contain a particular key-in-storage. A BSM bit and a page bit in the processor request address are put into the high-order field of the SP address register to control the selection of a group, so that alternate pages have their keys-in-storage put in different groups in a pair of groups in a SP array.

Key-in-storage accesses may be overlapped between different groups in an array.

When a request received from the XI bus has its key-in-storage found in one array, the key-in-storage is transmitted on the XI bus to the SC which sent the request.

Claims

1. Reconfigurable storage protection (SP) array control means for a main storage having BSMs (basic storage modules) organizable on a plural BSM interleaved basis, a storage request register receiving the absolute address of each storage request, means for testing each SP key for determining the permissability of each access request to main storage, and prohibiting a requested main storage access when the key is violated, comprising:

a plurality of SP groups comprising the SP array, each group having at least one array chip,

at least one SP address register for receiving bits of each absolute address in the storage request register, the absolute address having;

a BSM bit position which switches at main storage boundaries equal to the size of a BSM, and a block-related bit position which switches at main storage boundaries equal to an integral multiple of the size of a block, means connecting the bit positions of the absolute address in the storage request register to corresponding bit positions in the SP address register in the absolute address sequence of bits except that the block-related bit position is connected out-of-sequence to adjacently follow the BSM bit position in the SP address register, the SP address register being divided into at least a high-order field and a low-order field, the high-order field having both the BSM bit position and the block-related bit position,

decoder means in each SP group having an input connected to the low-order field of the SP address register, the decoder output connected to the array chip in the same SP group for locating an SP entry in the group,

a range identifier register in each SP group containing a value defining a range related to the size of a BSM,

a comparator in each SP group having one input connected to the high-order field in the SP address register, another input to the comparator connected to the range identifier register in the same SP group to select a required one of the SP groups in response to a storage request,

gating means with each SP group connected to the output of the comparator and to the output of the chip in the same SP group for outputting the SP entry located by the decoder means required by the storage request,

array output registering means, and

means for connecting the gating means of all SP groups in the array to the input to the array output registering means to output a selected SP entry.

2. Reconfigurable storage protection array control means, as defined in claim 1, in which:

each SP group further comprises a plurality of array chips,

the gating means further comprises a chip output gate for each chip,

an intermediate field is formed in the SP address register between the high-order field and the low-order field,

the decoder means comprises a chip decoder connected to the intermediate field for selecting a particular chip output gate, and a location decoder connected to the low-order field for locating an entry in the chip connected to the particular chip output gate, and

the gating means outputting the selected chip output gate to the array output registering means only in response to an output from the comparator.

3. Reconfigurable SP array control means as defined in claim 1, in which:

a processor console loads a different BSM range value into range identifier register, and

whereby the SP groups in the SP array operate associatively in relation to the requests.

4. Storage protect (SP) hardware having a plurality of SP entries for operating with main storage request addresses, in which each SP entry contains a protect key for a main storage block, main storage being organized with a plurality of modules providing a sequence of absolute addresses, and means for accessing main storage for data at a required storage request address, means for testing each SP key for determining the permissability of each access request to main storage, and prohibiting the requested main storage access when the SP key is violated, the SP hardware comprising:

a plurality of SP array groups for containing the SP entries,

SP register means for receiving each required storage request address being provided to main storage,

an address range register being provided in each array group for relating the SP arrays to an assignment of absolute addresses in the respective modules of main storage,

comparator means in each array group having one input for receiving a high-order part of the storage request address to main storage and having another input being connected to the address range register in the respective SP array group to select the associated SP array group upon an equal comparison,

decoder means with each array group for receiving a remaining low-order part of the storage request address to locate a SP entry in the selected array group at the same time that the storage request address is having requested data accessed in a requested module in main storage by the accessing means,

whereby a flexible hardware relationship is obtained between the SP hardware and hardware entities comprising main storage.

5. SP hardware for operating with main storage request addresses as defined in claim 4, further comprising:

each SP array group having a store array with a plurality of rows of SP entries arranged into a plurality of columns,

the decoder means selecting a SP entry in the store array by two dimensional selection by separating the low-order part of the storage request address into an upper section and a lower section which respectively address a column and row in the store array,

whereby any SP array group can be assigned to protect the accessing of data in any of plural subsets of contiguous addresses in main storage by loading a subset address into the address range register in the SP array group.

6. SP hardware for operating with main storage request addresses as defined in claim 5, the decoding means for each SP array group further comprising:

a first decoder receiving the lower section of the low-order part of the storage request address to select a row of SP entries in the store array of a selected array group,

a second decoder receiving the upper section of the low-order part of the storage request address to select the column and thereby a required SP entry in the selected row in the store array.