Method and signal processor for frequency analysis of time domain signals
First Claim
1. A processor for processing input data comprising N discrete samples ai (i=0,1,2, . . . , N-1) of a quantized time domain signal having real components aiR and imaginary components aiI in order to determine the frequency content thereof, said processor having a computational stage comprising:
- means connected to receive signals representing the real and imaginary components for calculating sums and differences of the real components of the input data and for calculating sums and differences of the imaginary components of the input data;
first data storage means for storing said sums and differences of the real and imaginary components of the input data and for retrieving the stored sums and differences of the real and imaginary components in a first predetermined order;
means connected to receive said retrieved sums and differences of the real and imaginary components, in said first predetermined order, for multiplying the retrieved sums and differences by predetermined constant values and for summing the products with at least some of the retrieved sums and differences to produce partial sums of the real and imaginary components;
second data storage means for storing the partial sums as they are produced and for retrieving the stored partial sums in accordance with a second predetermined order of retrieval in order to separately retrieve the partial sums of the real and imaginary components, respectively; and
means for calculating the sums and differences of the partial sums of the real components and the imaginary components of the data retrieved from said second storage means to produce real and imaginary output data representating the frequency content of the time domain signal.
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Abstract
A signal processor and method for processing N discrete samples of a quantized time domain signal to determine the frequency content or frequency spectrum of the time domain signal. Real and imaginary components of the quantized signal are processed in accordance with a decomposition technique that eliminates considerable hardware and reduces processing time. In a multiple stage processor, interstage multipliers are eliminated. One such disclosed processor includes a first data memory stage for storing the discrete samples of the quantized time domain signal and for retrieving the stored samples in a predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof. An L-point computational stage receives the retrieved samples of the quantized time domain signal and calculates real and imaginary output signals representing the solution to an L-point discrete Fourier transform. A second data memory stage stores the real and imaginary output signals from said L-point computational stage. An M point computational stage, where N=LM and L and M are relatively prime numbers, receives the retrieved output signals and calculates real and imaginary output signals representing the solution to an LM point discrete Fourier transform.
31 Citations
54 Claims
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1. A processor for processing input data comprising N discrete samples ai (i=0,1,2, . . . , N-1) of a quantized time domain signal having real components aiR and imaginary components aiI in order to determine the frequency content thereof, said processor having a computational stage comprising:
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means connected to receive signals representing the real and imaginary components for calculating sums and differences of the real components of the input data and for calculating sums and differences of the imaginary components of the input data; first data storage means for storing said sums and differences of the real and imaginary components of the input data and for retrieving the stored sums and differences of the real and imaginary components in a first predetermined order; means connected to receive said retrieved sums and differences of the real and imaginary components, in said first predetermined order, for multiplying the retrieved sums and differences by predetermined constant values and for summing the products with at least some of the retrieved sums and differences to produce partial sums of the real and imaginary components; second data storage means for storing the partial sums as they are produced and for retrieving the stored partial sums in accordance with a second predetermined order of retrieval in order to separately retrieve the partial sums of the real and imaginary components, respectively; and means for calculating the sums and differences of the partial sums of the real components and the imaginary components of the data retrieved from said second storage means to produce real and imaginary output data representating the frequency content of the time domain signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 31, 32, 33, 34, 35, 36)
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28. A processor for processing N discrete samples of a quantized time domain signal to determine the frequency content thereof comprising:
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a first data memory stage for storing the discrete samples of the quantized time domain signal and for retrieving said stored samples in a predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof; an L-point computational stage receiving the retrieved samples of the quantized time domain signal from said first data memory stage and calculating real and imaginary output signals representing the solution to an L-point Discrete Fourier Transform; a second data memory stage for storing and retrieving the real and imaginary output signals from said L-point computational stage; and an M-point computational stage, where N=LM and L and M are relatively prime numbers, receiving the retrieved real and imaginary output signals from said second data memory stage and calculating real and imaginary output signals representing the solution to an LM point Discrete Fourier Transform. - View Dependent Claims (29)
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30. A method for processing a time domain signal to determine the frequency content thereof, comprising the steps of:
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(a) quantizing the time domain signal to produce N discrete input data samples ai (i=0,1,2 . . . ,N-1) having real components aiR and imaginary components aiI ; (b) calculating and storing sums and differences of the real components of the input data samples; (c) calculating and storing sums and differences of the imaginary components of the input of data samples; (d) retrieving the stored sums and differences of the real and imaginary components in accordance with a first predetermined order of retrieval; (e) multiplying the retrieved sums and differences of the real and imaginary components, in the order of retrieval, by predetermined constant values and summing the products with at least some of the retrieved sums and differences to produce partial sums of the real and imaginary components; (f) storing the partial sums as they are produced; (g) retrieving the stored partial sums in accordance with a second predetermined order of retrieval in order to separately retrieve the partial sums of the real and imaginary components; and (h) calculating the sums and differences of the retrieved partial sums of the real components and the retrieved partial sums of the imaginary components to produce real and imaginary output data representing the frequency content of the time domain signal. - View Dependent Claims (37, 38)
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39. A processor for processing N discrete samples of a quantized time domain signal to determine the frequency content thereof comprising:
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a first data memory stage for storing the discrete samples of the quantized time domain signal and for retrieving said stored samples in a first predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof; an L1 -point computational stage receiving the retrieved samples of the quantized time domain signal from said first data memory stage and calculating real and imaginary output signals representing the solution to an L1 -point Discrete Fourier Transform; a second data memory stage for storing the real and imaginary output signals from said L1 -point computational stage and for retrieving said stored signals in a second predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof; an L2 -point computational stage receiving the retrieved signals from said second data memory stage and calculating real and imaginary output signals representing the solution to an L1 ·
L2 -point Discrete Fourier Transform;a third data memory stage for storing and retrieving the real and imaginary output signals from said L2 -point computational stage; an L3 -point computational stage receiving the retrieved real and imaginary output signals from said third data memory stage and calculating real and imaginary output signals representing the solution to an L1 ·
L2 ·
L3 -point Discrete Fourier Transform; anda fourth data memory stage for storing and retrieving the real and imaginary output signals from said L3 -point computational stage; wherein N=L1 ·
L2 ·
L3 and further wherein L1, L2 and L3 are relatively prime numbers. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46)
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47. A processor for processing input data comprising three discrete samples a0, a1, a2 of a quantized time domain signal having real components a0R, a1R, a2R and imaginary components a0I, a1I, a2I in order to determine the frequency components A0, A1, A2 of the Discrete Fourier Transform of said input data, said processor comprising:
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first, second, third, fourth, fifth and sixth adders; first and second inverters; first and second programmable read-only memories; first, second and third registers; and a counter; said first adder selectively receiving the real and imaginary components of said sample a0 and receiving output signals from said second adder; and said first register receiving output signals from said first adder, the output of said first register being the frequency component A0 ; said second adder selectively receiving the real and imaginary components of said samples a1, a2 ; said first programmable read-only memory receiving output signals from said second adder; said second register receiving output signals from said first programmable read-only memory; said fourth adder receiving output signals from said first and second registers; and said fifth adder receiving output signals from said fourth adder and from said third register, the output from said fifth adder being the frequency component A1 ; said first inverter selectively receiving the real and imaginary components of said sample a2 ; said third adder selectively receiving the real and imaginary components of the sample a1, said third adder receiving output signals from said first inverter, and said third adder receiving a constant; said second programmable read-only memory receiving output signals from said third adder; said third register receiving output signals from said second programmable read-only memory and from said counter; said second inverter receiving output signals from said third register; and said sixth adder receiving a constant and receiving output signals from said second inverter and from said fourth adder, the output of said sixth adder being the frequency component A2.
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48. A processor for processing input data comprising five discrete samples ai, i=0,1,2,3,4, of a quantized time domain signal having real components aiR and imaginary components aiI in order to determine frequency components of the Discrete Fourier Transform of said input data, said processor comprising:
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seventeen adders; seven inverters; five programmable read-only memories; six registers; and one counter; wherein a first adder selectively receives the real and imaginary components of said sample ao and receives output signals from a third adder; and wherein a first register receives output signals from said first adder, the output of said first register being frequency components AOI, AOR ; wherein a second adder selectively receives the real and imaginary components of said samples a1, a4 ; wherein said third adder receives output signals from said second adder and from a sixth adder; wherein a first programmable read-only memory receives output signals from said third adder; wherein a second register receives output signals from said first programmable read-only memory; wherein a ninth adder receives output signals from said first and second registers; wherein a tenth adder receives output signals from said ninth adder and from a fourth register; and wherein an eleventh adder receives output signals from said tenth adder and from a twelfth adder, the output of said eleventh adder being frequency components A4I, A1R ; wherein a first inverter selectively receives the real and imaginary components of said sample a4 ; wherein a fourth adder selectively receives the real and imaginary components of said sample a1, receives a constant and receives output signals from said first inverter; wherein a fifth adder receives output signals from said fourth adder and from an eighth adder; wherein a second programmable read-only memory receives output signals from said fifth adder; wherein a third register receives output signals from said second programmable read-only memory and from said counter; wherein said twelfth adder receives output signals from said third register and from a sixth register; wherein a fifth programmable read-only memory receives output signals from said fourth adder; wherein said sixth register receives output signals from said counter and from said fifth programmable readonly memory; wherein a second inverter receives output signals from said twelfth adder; and wherein a thirteenth adder receives output signals from said tenth adder and from said second inverter, the output of said thirteenth adder being frequency components A1I, A4R ; wherein said sixth adder selectively receives the real and imaginary components of said samples a2, a3 ; wherein a third inverter receives output signals from said sixth adder; wherein a seventh adder receives a constant and receives output signals from said third inverter; wherein a third programmable read-only memory receives output signals from said seventh adder; wherein said fourth register receives output signals from said third programmable read-only memory; wherein a fourth inverter receives output signals from said fourth register; wherein a fourteenth adder receives a constant and receives output signals from said ninth adder and said fourth inverter; and wherein a fifteenth adder receives output signals from said fourteenth adder and from a sixteenth adder, the output of said fifteenth adder being frequency components A3I, A2R ; wherein a fifth inverter selectively receives the real and imaginary components of said sample a3 ; wherein said eighth adder selectively receives the real and imaginary components of said sample a2, receives a constant and receives output signals from said fifth inverter; wherein a fourth programmable read-only memory receives output signals from said eighth adder; wherein a fifth register receives output signals from said counter and from said fourth programmable read-only memory; wherein a sixth inverter receives output signals from said fifth register; wherein said sixteenth adder receives a constant and receives output signals from said third register and said sixth inverter; wherein a seventh inverter receives output signals from said sixteenth adder; and wherein a seventeenth adder receives a constant and receives output signals from said fourteenth adder and said seventh inverter, the output of said seventeenth adder being frequency components A2I, A3R.
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49. A processor for processing input data comprising eight discrete samples ai, i=0,1,2, . . . ,7, of a quantized time domain signal having real components aiR and imaginary components aiI in order to determine frequency components of the Discrete Fourier Transform of said input data, said processor comprising:
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twenty-six adders; thirteen inverters; first and second programmable read-only memories; eight registers; and one counter; wherein a first adder selectively receives the real and imaginary components of said samples a0, a4 ; wherein a second adder receives output signals from said first adder and from a fourth adder; wherein a first register receives output signals from said second adder; and wherein a fifteenth adder receives output signals from said first register and from a fifth register, the output of said fifteenth adder being frequency components A0I, A0R ; wherein a first inverter selectively receives the real and imaginary components of said sample a4 ; wherein a third adder selectively receives the real and imaginary components of said sample a0, receives a constant and receives output signals from said first inverter; wherein a second register receives output signals from said third adder; wherein a sixteenth adder receives output signals from said second register and from a fourth register; and wherein a seventeenth adder receives output signals from said sixteenth adder and from a twenty-second adder, the output of said seventeenth adder being frequency components A7I, A1R ; wherein said fourth adder selectively receives the real and imaginary components of said samples a2, a6 ; wherein a second inverter receives output signals from said fourth adder; wherein a fifth adder receives a constant and receives output signals from said first adder and said second inverter; wherein a third register receives output signals from said fifth adder; and wherein an eighteenth adder receives output signals from said third register and from an eighth register, the output of said eighteenth adder being frequency components A6I, A2R ; wherein a third inverter selectively receives the real and imaginary components of said sample a6 ; wherein a sixth adder selectively receives the real and imaginary components of said sample a2, receives a constant and receives output signals from said third inverter; wherein said fourth register receives output signals from said sixth adder; wherein a fourth inverter receives output signals from said fourth register; wherein a nineteenth adder receives a constant and receives output signals from said second register and from said fourth inverter; and wherein a twentieth adder receives output signals from said nineteenth adder and from a twenty-fourth adder, the output of said twentieth adder being frequency components A1I, A7R ; wherein a seventh adder selectively receives the real and imaginary components of said samples a1, a7 ; wherein an eighth adder receives output signals from said seventh adder and from an eleventh adder; wherein said fifth register receives output signals from said eighth adder; wherein a fifth inverter receives output signals from said fifth register; and wherein a twenty-first adder receives a constant and receives output signals from said first register and said fifth inverter, the output of said twenty-first adder being frequency components A4I, A4R ; wherein a sixth inverter selectively receives the real and imaginary components of said sample a7 ; wherein a ninth adder selectively receives the real and imaginary components of said sample a1, receives a constant and receives output signals from said sixth inverter; wherein a tenth adder receives output signals from said ninth adder and from a thirteenth adder; wherein said first programmable read-only memory receives output signals from said tenth adder; wherein a sixth register receives output signals from said first programmable read-only memory and from said counter; wherein said twenty-second adder receives output signals from said sixth register and from a seventh register; wherein a seventh inverter receives output signals from said twenty-second adder; and wherein a twenty-third adder receives a constant and receives output signals from said sixteenth adder and said seventh inverter, the output of said twenty-third adder being frequency components A3I, A5R ; wherein said eleventh adder selectively receives the real and imaginary components of said samples a3, a5 ; wherein an eighth inverter receives output signals from said eleventh adder; wherein a twelfth adder receives a constant and receives output signals from said seventh adder and said eighth inverter; wherein said second programmable read-only memory receives output signals from said twelfth adder; wherein said seventh register receives output signals from said second programmable read-only memory; wherein said twenty-fourth adder receives a constant and receives output signals from said seventh register and from a thirteenth inverter, said thirteenth inverter receiving output signals from said sixth register; wherein a ninth inverter receives output signals from said twenty-fourth adder; and wherein a twenty-fifth adder receives a constant and receives output signals from said nineteenth adder and said ninth inverter, the output of said twenty-fifth adder being frequency components A5I, A3R ; wherein a tenth inverter selectively receives the real and imaginary components of said samples a5 ; wherein said thirteenth adder selectively receives the real and imaginary components of said sample a3, receives a constant and receives output signals from said tenth inverter; wherein an eleventh inverter receives output signals from said thirteenth adder; wherein a fourteenth adder receives a constant and receives output signals from said ninth adder and said eleventh inverter; wherein said eighth register receives output signals from said fourteenth adder; wherein a twelfth inverter receives output signals from said eighth register; and wherein a twenty-sixth adder receives a constant and receives output signals from said third register and from said twelfth inverter, the output of said twenty-sixth adder being frequency components A2I, A6R.
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50. A method for processing a time domain signal to determine the frequency content thereof, comprising the steps of:
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(a) quantizing the time domain signal to produce N discrete input data samples an (n=0,1,2, . . . ,N-1) having real components anR and imaginary components anI such that N=L1 ·
L2 ·
L3 where L1, L2 and L3 are relatively prime numbers;(b) storing said discrete samples in a first data memory stage and retrieving said stored samples in a first predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof; (c) receiving the retrieved samples in said first predetermined order in an L1 -point computational stage and calculating real and imaginary output signal representing the solution to an L1 -point Discrete Fourier Transform; (d) storing the real and imaginary output signals of the L1 -point computational stage in a second data memory stage and retrieving said stored signals in a second predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof; (e) receiving the retrieved signals in said second predetermined order in an L2 -point computational stage and calculating real and imaginary output signals representing the solution to an L1 ·
L2 -point Discrete Fourier Transform;(f) storing the real and imaginary output signals of the L2 -point computational stage in a third data memory stage and retrieving said stored signals; (g) receiving the retrieved signals from said third data memory stage in an L3 -point computational stage and calculating real and imaginary output signals representing the solution to an L1 ·
L2 ·
L3 -point Discrete Fourier Transform; and(h) storing the real and imaginary output signals of the L3 -point computational stage in a fourth data memory stage. - View Dependent Claims (51, 52, 53, 54)
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Specification