Data mover

• US 4,296,465 A
• Filed: 11/03/1977
• Issued: 10/20/1981
• Est. Priority Date: 11/03/1977
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Lemak, Nicholas S.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/848,172
• Time in Patent Office: 1,447 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/316
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache

Abstract

A data mover for moving blocks of data stored in a first location of the working store of a data processing system to a second location in the working store. The data mover is provided with the necessary registers, switches, counters and control circuits to issue read and write commands to the working store, to receive and store in registers data read out of the working store as the result of its having issued a read command, and to write data read out of working store and stored in its registers in response to a read command issued by the data mover into another location in the working store. These steps are repeated until a block, measured in thousands, of data words has been moved from the first to the second location. The address preparation circuits of the high speed multiplexer of the data processing system through which the data mover communicates with the working store of the system is used to provide a substitute memory command for one of the two types of memory commands issued by the data mover. Between the time the data mover issues a read command, and receives back from memory the data read out of memory in response to such a command, the data mover can issue a write command and transfer to the high speed multiplexer data received in response to the previous read command.

Claims

1. A data mover comprising:

a data in bus;

a data out bus;

a control bus;

data register means connected to the data in bus for storing at least one data word;

control register means connected to the data in bus for storing at least one control word;

means connected to the data out bus for issuing memory read commands and memory write commands; and

control means connected to the control bus, to the data register means, and to the means for issuing memory commands for causing the means for issuing memory commands to issue a write command after issuing a read command on the data out bus only if a data word is stored in said data register means in response to a previously issued read command and to issue the data words stored in the data register means on the data out bus immediately following the issuing of write command.

2. The data mover of claim 1 which also comprises throttle means connected to the control means for limiting the maximum rate at which the data mover can transmit and receive data words.

3. A data mover comprising:

data register means for storing a data word, control register means for storing a control word, a data out bus, means for transmitting to the data out bus a memory read command derived from information stored in said control register means, means for transmitting to the data out bus a memory write command derived from information stored in said control register means and the data word stored in said data register means only if a data word is stored in said data register means in response to a previously transmitted read command.

4. A data mover comprising:

a data in bus;

a data out bus;

a control bus;

data register means connected to the data in bus having the capability of storing two data words;

control register means connected to the data in bus for storing at least one data control word;

means for issuing memory read commands and memory write commands connected to the data out bus; and

control means connected to the data in bus, the control bus, the data register means, control register means, and the means for issuing memory commands;

said control means causing the means for issuing memory commands to issue on the data out bus a write command after issuing a read command on the data out bus only if a data word is stored in the data register means in response to a previously issued read command and to issue on the data out bus the data word stored in the data register means immediately following the issuing of a write command.

5. The data mover of claim 4 which also comprises a source of clock pulses, a sequence counter connected to the control means, the control register means and to the source of clock pulses for enabling the data mover to issue memory commands only after a predetermined number of clock pulses has been counted by the counter after the issuance of a preceding command.

6. The data mover of claim 5 in which the predetermined number of clock pulses is specified in the data control word stored in the control register means.

7. In a data processing system having a memory for storing a plurality of data words, said memory having a buffer portion and a user portion;

a memory controller;

a systems interface unit;

the memory controller connecting the memory to the systems interface unit;

a high speed multiplexer connected to the systems interface unit and having a plurality of ports, said multiplexer having the capability of issuing indirect memory commands; and

an input/output processor connected to the systems interface unit;

the improvements comprising;

a data mover connected to a port of the high speed multiplexer for moving blocks of data words from the buffer portion of the memory to the user portion, said data mover having a data in bus, a data out bus, and a control bus connected to said port of the high speed multiplexer;

data register means connected to the data in bus for storing a data word;

control register means connected to the data in bus for storing a data control word;

means for producing an address in memory connected to the data in bus;

switch means connected to the means for producing an address and the data out bus for applying to the data out bus of the data mover read and write memory commands including addresses produced by said means for producing an address;

a control block connected to the control bus, the data and control register means, the means for producing an address, and the switch means;

said control block producing control signals;

said switch means, in response to control signals from the control block producing a first read command addressed to the buffer portion of memory, and if no data word is stored in the data register after the first read command is issued, for issuing a second read command to the next memory location in the buffer portion, said switch means in response to signals from the control block applying a write command to the data out bus and the data word stored in the data register means to the data out bus, and repetitively issuing read and write commands and data words stored in the data register means until a block of data words is moved from the buffer area of memory to the user area.

8. In the data processing system of claim 7 in which the high speed multiplexer issues an indirect memory command for one type of memory command issued by the data mover.

9. In the data processing system of claim 8 in which the high speed multiplexer issues indirect write commands the address portion of which is in the user portion of the memory.

10. In a data processing system including multiplexer means for controlling a plurality of peripheral devices coupled to the multiplexer, memory means for storing data words said memory means having a user portion and a buffer portion, input/output processor means for generating instruction data words, and means for interconnecting the memory means, the processor means and the multiplexer means;

said multiplexer means including register means, said register means storing data words transferred to said mutliplexer means and for preparing and issuing memory commands; and

control means for controlling the operation of the multiplexer means;

the improvements comprising;

a data mover, said data mover having data register means for storing a data word transferred to the data mover from the multiplexer means;

control register means for storing at least one control word transferred to the data mover from the multiplexer means;

means for issuing memory read and write commands to the mutliplexer means;

means for issuing data words stored in the data register means to the multiplexer means; and

data mover control means connected to the multiplexer for causing the means for issuing memory commands of the data mover to issue read and write types of memory commands, said means for issuing memory commands of the data mover issuing a read command followed by a write command if a data word is stored in the data register means in response to a previously issued read command, and to issue the data word stored in the data register means to the multiplexer means immediately following the issuing of a write command;

said multiplexer means issuing a memory command which the multiplexer substitutes for one type of memory command issued by the data mover.

11. In the data processing system of claim 10 in which the type of memory command issued by the data mover which the multiplexer substitutes memory commands produced by the multiplexer means are write commands.

12. In the data processing system of claim 11 in which the write commands issued by the multiplexer means are addressed to the user portion of the memory means and the read commands to the buffer portion.

13. In the data processing system of claim 10 in which the data mover includes throttle means connected to the data mover control means for limiting the maximum rate at which the data mover can issue memory commands to the multiplexer means.

14. In the data processing system of claim 13 in which the throttle means includes a sequence counter which under program control requires "n", where "n" is an integer, clock periods to elapse between the issuance of memory commands.

15. In the data processing system of claim 14 in which "n" is the range of from 4 to 12.

16. A data processing system comprising:

a systems interface unit (SIU) having a plurality of ports, said SIU having the capability in response to control signals applied to it of transmitting data words from one port to another;

a memory controller connected to a memory port of the SIU;

a random access memory connected to the memory controller and adapted to store data words in the memory and to retrieve data words previously stored in the memory;

said memory having a buffer portion and a user portion;

said memory controller causing said memory, in response to write commands transmitted to the memory, to store data words in a given memory location and in response to read commands to read data words out of memory which were stored at a given location in memory;

a high speed multiplexer (HSMX) connected to a port of the SIU, said HSMX having a plurality of channels, said channels adapted to have mass storage devices connected thereto;

said HSMX having control register means;

means for producing read or write memory commands using information stored in the control register means;

register means for storing data words transmitted to the multiplexer by a device connected to a channel; and

means for transmitting data words stored in said register means to the SIU;

an IOPP connected to one of the ports of the SIU and having the capability under program control of issuing commands to the high speed multiplexer and devices connected to a channel of the multiplexer; and

a data mover having a data in bus, a data out bus, and a control bus, said buses being connected to the high speed multiplexer;

said data mover having data registers connected to the data in bus for storing data words transmitted to the data mover from the high speed multiplexer;

control register means connected to the data in bus for storing commands transmitted to the data mover from the IOPP;

memory command preparing means connected to the data out bus for issuing memory read and memory write commands; and

control means connected to the control bus, to the data register means, and to the memory command preparing means for causing the memory command preparing means to prepare and issue a memory read command to the memory in response to command words transmitted to the data mover from the IOPP, said memory read command including the address in memory of a particular location in the buffer portion of memory, issuing a second read command to the buffer portion of memory if no data words are stored in the data registers; and

for issuing a write command to the user portion of memory and at least one data word stored in the data registers of the data mover before data words read out of memory pursuant to a previously issued read command have been received by the data mover and stored in the data register means thereof.

17. In the data processing system of claim 16 in which the HSMX issues one type of memory command addressed to one portion of the random access memory and forwards memory commands of the other type issued by the data mover addressed to the other portion of the random access memory.

18. In the data processing system of claim 17 in which the HSMX issues write memory commands addressed to the user portion of memory to the SIU and forwards read memory commands issued by the data mover to the SIU.