TV Game apparatus

• US 4,296,930 A
• Filed: 07/05/1977
• Issued: 10/27/1981
• Est. Priority Date: 11/26/1975
• Status: Expired due to Term

• Current Assignee: Midway Amusement Games, LLC (Midway Games Inc.)
• Original Assignee: Bally Manufacturing Corp. (Park Hotels & Resorts Inc.)
• Inventors: Frederiksen, Jeffrey E.
• Primary Examiner(s): Hum, Vance Y.
• Application Number:
  US05/812,662
• Time in Patent Office: 1,575 Days
• Field of Search: 273/85 G, 273/101.2, 273/DIG. 28, 340/324 AD, 358/142, 364/200 MS File, 364/900 MS File, 364/410
• US Class Current: 463/31
• CPC Class Codes: A63F 13/00 Video games, i.e. games using an electronically generated display having two or more dimensions gaming systems which provide a financial reward G07F17/32
• CPC Class Codes: A63F 13/24 Constructional details thereof, e.g. game controllers with detachable joystick handles
• CPC Class Codes: A63F 13/837 Shooting of targets
• CPC Class Codes: A63F 2300/203 Image generating hardware

Abstract

A TV-type game employs a raster screen television for presenting game symbols. Player operated control switches are encoded to move the symbols. A microprocessor reads the switches. A dually addressed random access memory is employed as the interfacing between the screen and the processor which otherwise function as essentially separate and distinct devices. The memory provides a static storage of the screen pattern for each point in the raster lines with a portion assigned as a processor scratch pad. The memory may be dynamic with periodic refreshing and constructed with individual chips for each of the several bits in a word. The chips are grouped for alternate refreshing and powered during access periods. The processor updates the memory during idle display access periods. The memory is accessed in multiple bit words or bytes for display and processing. For display, a parallel to serial output latch is employed. The previous symbol position and pose is stored in the scratch pad and is erased and rewritten in a new position and pose. The controls may provide encoding. A hardwired bit shifter with programmed shift level rapidly shifts the symbol bits before placing in memory. A high speed memory and low speed processor are shown with separate clocks and a special synchronizer unit.

Claims

1. A player-operated game apparatus for use with a display screen means having an intensity control means for varying the intensities of picture elements for the presentation of movable symbols on a screen, said apparatus comprising player-operated means including input elements adapted to be operated by a player and signal means actuable by said input elements for affecting the display of symbols and initiating interaction of the player with the symbols on the screen;

random access memory for storing in a digital form a set of digital bits representing the intensities necessary for generating a display on said screen and locating the symbols within the display;

display controller means for addressing said random access memory and reading the set of bits in the random access memory in time-spaced read periods separated by reading idle periods, in each of which read periods one or more bits associated with a desired display are read from the random access memory, said display controller means being adapted for connection to said intensity control means of the display means to transmit the bits to said intensity control means to present the desired display stored in said random access memory;

a microprocessor;

program means;

communicating port means for connecting the signal means of the player-operated means to the microprocessor;

said microprocessor having means for accessing said program means and means for reading from and writing to said random access memory to represent symbols in response to said signal means and said program means wherein the microprocessor revises and controls interaction of the symbols within the display;

control means operatively coupling the random access memory to the microprocessor during said reading idle periods to change said random access memory between said read periods;

means for reading bits associated with the desired display from the random access memory in parallel groups defined by a predetermined number of bits during each of the reading periods;

serializing means serially transmitting a parallel group of bits to the intensity control means;

said means for reading from and writing to said random access memory including means for accessing the random access memory a parallel group of bits at a time whereby the microprocessor modifies digital bits in the random access memory a parallel group of bits at a time;

shifting means operatively coupled to the microprocessor for receiving therefrom parallel groups of bits, and for shifting the bits of the parallel groups of bits a number of bit positions as determined by the microprocessor; and

means for transferring the parallel groups of bits so shifted from the shifting means to the random access memory so that smooth appearing continuous movements of the symbols on the display is provided.

5. The apparatus according to claim 1, 2 or 3 wherein said display controller means further includes a memory address generating means and a control signal means for signaling the initiation of a read period;

said microprocesssor includes a memory address bus; and

said control means comprises an address multiplexer operatively coupled to the random access memory and also operatively coupled to the memory address generating means of the display controller means and to the memory address bus of the microprocessor and operatively coupled to the control signal means of the display controller means to control the coupling of the random access memory to the display controller means and to the microprocessor so that said display controller means can address said random access memory during said read periods and said microprocessor is operatively coupled to said random access memory only during said reading idle periods.

6. The apparatus of claim 5 wherein each group of bits in the random access memory has an address and the memory address generating means comprises a plurality of counters for generating sequential memory addresses whereby each group of bits may be addressed and read in sequential fashion.

7. The apparatus of claim 6 wherein the set of bits in the random access memory is arranged in matrix form so that each plurality of bits has a horizontal and a vertical address and the plurality of counters includes a horizontal counter for generating the horizontal address and a vertical counter for generating the vertical address of each plurality of bits.

8. The apparatus of claim 7 wherein said display means includes a screen having a matrix pattern defined by pluralities of dots, said plurality of dots each having horizontal and vertical coordinates on the screen corresponding to the horizontal and vertical addresses of a plurality of bits in the random access memory.

9. The apparatus according to claims 1, 2 or 3 wherein said program means includes symbol memory means having a set of bits representing the intensities necessary for generating for each symbol a display of said symbol on said screen.

10. The apparatus of claim 9 wherein a symbol has a plurality of different poses, said symbol memory means having a set of digital bits representing the intensities necessary for generating a display of the plurality of poses on said screen for said symbols having a plurality of poses.

11. In the apparatus of claim 1, wherein a group of bits comprises a byte and two successive bytes are read from the microprocessor to the shifting means, said shifting means comprising means for shifting the two bytes and for selecting appropriate bits from the two bytes to form an appropriate byte to store in the random access memory.

12. The apparatus of claim 11 wherein said symbols are defined by a selected block within the random access memory, at least one of said symbols and blocks being a plurality of bytes wide, said shifting means comprising a hardwired bit shifter for shifting the bits in a byte for transfer to a block within said random access memory and having shift level means for setting the number of bit shifts for each byte;

said microprocessor being connected to the shift level means and setting said shift level means for the number of bit shifts to locate the bits in the proper random access memory blocks.

13. The apparatus according to claims 1 or 1, 6 wherein said display controller means includes an interrupt signal means;

said microprocessor including interrupt port means connected to the interrupt signal means; and

said microprocessor being responsive to said interrupt signal means for writing of bits associated with a symbol in the random access memory.

14. The apparatus fo claim 13 wherein the display means generates time-spaced display frames, and the microprocessor erases the bits associated with a symbol and writes in the random access memory bits associated with a symbol during periods of alternate frames.

15. The apparatus of claim 13 wherein said display controller means includes a sync and blank signal means for blanking the scanning beam during horizontal and vertical retrace, said reading idle period occurring during said horizontal and vertical retrace, and a clock means connected to actuate the sync and blank signal means and the interrupt signal means.

16. The apparatus according to claim 1, 2 or 3 comprising means for operating said display controller means at a first rate and means for operating said microprocessor at a second rate whereby said microprocessor can operate at a relatively slow rate while maintaining a relatively complete and accurate presentation of a symbol moving within the display on a relatively high speed raster scan screen.

17. The apparatus of claim 1 further including a data latch means for latching a plurality of bits from the random access memory to the microprocessor, and a synchronizing means controlled by the display controller means for setting of said latch means;

said microprocessor having a wait state established in response to a request for the random access memory and having a ready port connected to said synchronizing means; and

said synchronizing means having means connected to the ready port of the microprocessor for producing a ready signal upon the completion of setting of the latch means.

18. The apparatus according to claims 1, 2 or 3 wherein said random access memory includes a plurality of additional locations defining a scratch pad memory means.

19. The apparatus of claim 18 wherein a symbol may have a plurality of different poses, each of which is stored as bits in the program means;

and said microprocessor includes means for storing a representation of a last written symbol pose in the scratch pad memory means, for calculating a new symbol pose, and for storing bits representing the new symbol pose in said random access memory, whereby the symbol in the display is repositioned and redrawn to simulate realistic symbol movement.

20. The apparatus of claim 19 wherein said microprocessor in representing a new presentation of a symbol in the random access memory has means for completely erasing the bits of the previous symbol and for storing the bits of the new presentation of the symbol.

21. The apparatus according to claim 1, 2 or 3 wherein said microprocessor includes vectoring means for storing reference data for selected symbols in a previous display frame, and said microprocessor having means for storing bits representing a new symbol in said random access memory in accordance with the actuation of said signal means of the player-operated control means to move said symbols within the display in accordance with the movement of the player-operated means and the presentation in the previous display frame.

22. The apparatus according to claim 1, 2 or 3 including sets of player-operated means for each player, and having a game logic multiplexer having a plurality of multiple bit input means and a multiple bit output, each of said input means being connected to sample one set of said player-operated means in response to the microprocessor.

23. The apparatus of claim 1 wherein the serializing means comprises a parallel-to-serial latch.

24. The apparatus of claim 1 wherein the shifting means includes two cascaded latch stages.

25. The apparatus according to claims 1, 2 or 3 wherein the random access memory includes dynamic memory means for each location within said random access memory, said dynamic memory means being separated into a plurality of groups each of which groups produces said plurality of bits, and a clock driver for sequentially and cyclically enabling said plurality of groups.

26. The apparatus according to claims 1, 2 or 3 wherein said random access memory includes a plurality of memory chips arranged in columns, each column including a chip for each bit of the group of bits read, said memory chips being dynamic memory chips, a driver being connected to the chips in each column for alternately refreshing and enabling the columns of memory chips, and a logic means connecting said driver to said addressing means for refreshing and enabling of said columns of memory chips during the read periods so that a group of bits may be read from a column of memory chips during a read period.

2. A player-operated game apparatus for use with a display screen means having an intensity control means for varying the intensities of picture elements for the presentation of movable symbols on a screen, said apparatus comprising player-operated means including input elements adapted to be operated by a player and signal means actuable by said input elements for affecting the display of symbols and initiation interaction of the player with the symbols on the screen;

random access memory for storing in a digital form a set of digital bits representing the intensities necessary for generating a display on said screen and locating the symbols within the display;

display controller means for addressing said random access memory and reading the set of bits in the random access memory in time-spaced read periods separated by reading idle periods, in each of which read periods one or more bits associated with a desired display are read from the random access memory, said display controller means being adapted for connection to said intensity control means of the display means to transmit the bits to said intensity control means to present the desired display stored in said random access memory;

a microprocessor;

program means;

communicating port means for connecting the signal means of the player-operated means to the microprocessor, said microprocessor having means for accessing said program means and means for reading from and writing to said random access memory to represent symbols in response to said signal means and said program means whereby the microprocessor revises and controls interaction of the symbols within the display;

control means operatively coupling the random access memory to the microprocessor during said reading idle periods to change said random access memory between said read periods; and

processing means operatively coupled to the microprocessor for receiving therefrom control signals and symbol signals representative of a symbol to be displayed on the display, the control signals activating the processing means for transforming the symbol signals to produce transformed symbol signals so that a symbol represented by the transformed symbol signals is different than a symbol represented by the symbol signals relative to the display, and for providing smooth appearing continuous movement of the symbols on the display.

4. The apparatus according to claim 2 or 3 wherein during each of the reading periods bits associated with the desired display are read from the random access memory in parallel groups defined by a predetermined number of bits.

3. A player-operated game apparatus for use with a display screen means having an intensity control means for varying the intensities of picture elements for the presentation of movable symbols on a screen, said apparatus comprising player-operated means including input elements adapted to be operated by a player and signal means actuable by said input elements for affecting the display of symbols and initiating interaction of the player with the symbols on the screen;

random access memory for storing in a digital form a set of digital bits representing the intensities necessary for generating a display on said screen and locating the symbols within the display;

display controller means for addressing said random access memory and reading the set of bits in the random access memory in time-spaced read periods separated by reading idle periods, in each of which read periods one or more bits associated with a desired display are read from the random access memory, said display controller means being adapted for connection to said intensity control means of the display means to transmit the bits to said intensity control means to present the desired display stored in said random access memory;

a microprocessor;

program means;

communicating port means for connecting the signal means of the player-operated means to the microprocessor;

said micrprocessor having means for accessing said program means and means for reading from and writing to said random access memory to represent symbols in response to said signal means and said program means whereby the microprocessor revises and controls interaction of the symbols within the display;

control means operatively coupling the random access memory to the microprocessor during said reading idle periods to change said random access memory between said read periods;

interrupt signal means for generating a pair of interrupt sigals which divides the screen into two parts, means for connecting the interrupt signal means to the microprocessor for transferring the pair of interrupt signals thereto so that digital bits of the random access memory representative of one part of the screen can be revised while digital bits of the random access memory representative of the other part of the screen are read to the intensity control means.