Analog waveform digitizer

• US 4,297,680 A
• Filed: 08/03/1979
• Issued: 10/27/1981
• Est. Priority Date: 08/03/1979
• Status: Expired due to Term

• Current Assignee: John Fluke Mfg. Co., Inc. (Fortive Corp.)
• Original Assignee: John Fluke Mfg. Co., Inc. (Fortive Corp.)
• Inventors: Koeman, Henriecus
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US06/063,521
• Time in Patent Office: 816 Days
• Field of Search: 340/347 M, 340/347 SH, 340/347 AD, 328/151, 328/114, 328/132, 358/133, 358/138, 358/261, 364/112, 307/353
• US Class Current: 341/123
• CPC Class Codes: G01R 13/342 for displaying periodic H.F. signals G01R13/345 takes precedence
• CPC Class Codes: G01R 17/04 in which the reference value is continuously or periodically swept over the range of values to be measured
• CPC Class Codes: G01R 19/257 using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method
• CPC Class Codes: H03M 1/50 with intermediate conversion to time interval H03M1/64 takes precedence

Abstract

A waveform digitizer particularly suitable for use in electronic test systems for analyzing and displaying analog signals is disclosed. A digitally derived reference voltage is compared with the analog signal to be digitized during a series of comparison sequences. Simultaneously with the start of each comparison sequence a digital clock is started. Each time the analog signal rises above, or drops below, the reference voltage a decision change detector produces an enable pulse. Each time an enable pulse occurs, a data word, having a portion related to the value of the digitally derived reference voltage and a portion related to the digital clock value, is stored and/or used to control a display. At the end of the first comparison sequence (determined when the digital clock value reaches a predetermined level) the reference voltage is incremented and a second comparison sequence started. These steps are repeated until the reference voltage reaches a predetermined level. The resulting set of digital words is digitized equivalent of the waveform of the analog signal.

Claims

1. A waveform digitizer for digitizing analog signals comprising:

reference voltage means for sequentially producing a series of digitallyderived reference voltages one-at-a-time, each reference voltage having a different voltage value;

comparison means coupled to said voltage reference means for sequentially comparing each of said series of digitally derived reference voltages with an analog signal whose waveform is to be digitized during a series of comparison sequences and producing a comparison pulse each time said reference voltage and the analog signal voltage cross during said comparison sequences;

timing means starting at the beginning of each comparison sequence for continuously producing a digital time signal during each comparison sequence; and

,

combining means coupled to said comparison means and said timing means for receiving said comparison pulses and said digital time signal and developing a digital word each time a comparison pulse is received, said digital word having a portion related to the value of the digitally derived reference voltage produced by said reference voltage means and a position related to the digital time signal present when said comparison pulse is received.

2. A waveform digitizer as claimed in claim 1 wherein said timing means comprises a time base oscillator started at the beginning of each comparison sequence and a time base counter for counting the output of said time base oscillator, said time base counter producing, in addition to said digital time signal, an output signal when said time base counter has counted up to a predetermined value.

3. A waveform digitizer as claimed in claim 2 wherein said reference voltage means comprises an amplitude counter and a first digital-to-analog converter connected to the output of said amlitude counter, the output of said digital-to-analog converter forming said series of digitally derived reference voltages, the increment input of said amplitude counter connected to receive the output signal produced by said time base counter when said time base counter has counted up to said predetermined value.

4. A waveform digitizer as claimed in claim 3 wherein said comparison means comprises:

a comparator having one input connected to receive said analog signal and the other input connected to receive said series of digitally derived reference voltages; and

,

a decision change detector connected to the output of said comparator for producing said comparison pulse when the analog signal voltage crosses said reference voltage during a comparison sequence.

5. A waveform digitizer as claimed in claim 4 wherein said combining means comprises:

an address increment counter having its increment input connected to the output of said decision change detector; and

,

a memory, the signal inputs of said memory connected to the output of said amplitude counter and the output of said time base counter carrying said digital time signal, the write input of said memory connected to the output of said decision change detector and the address inputof said memory connected to the output of said address increment counter.

6. A waveform digitizer as claimed in claim 4 wherein said combining means comprises:

an address increment counter having its increment input connected to the output of said decision change detector;

a flip-flop having one override control input connected to the output of said time base counter produced when said time base counter has counted up to said predetermined value and its clock input connected to the output of said decision change detector; and

,

a memory having its signal input connected to one output of said flip-flop and to the output of said time base counter carrying said digital time signal, its address input connected to the output of said address increment counter and its write input connected to the output of said decision change detector.

7. A waveform digitizer as claimed in claim 4 wherein said timing means also includes:

a time base trigger circuit, connected to receive a trigger condition signal and a trigger signal, for producing a set pulse when said trigger signal complies with the condition set by said trigger condition signal; and

,

a hold off trigger circuit connected to receive the set pulses produced by said time base trigger circuit, said hold off trigger circuit connected to said decision change detector so as to initialize said decision change detector and to said time base oscillator so as to start said time base oscillator upon the receipt of a set pulse from said time base trigger circuit, said hold off trigger circuit connected to said time base counter so as to be reset when said time base counter produces said output signal produced by said time base counter when said time base counter has counted up to said predetermined value.

8. A waveform digitizer as claimed in claim 5 wherein said combining means also comprises:

a second digital-to-analog converter havings its input connected to the output of said time base counter carrying said digital time signal; and

,

a X-Y display means having one of its X-Y control inputs connected to the output of said first digital-to-analog converter and the other of its X-Y control inputs connected to the output of said second digital-to-analog converter and having its image control input connected to the output of said decision change detector.

9. A waveform digitizer as claimed in claim 6 wherein said combining means comprises:

a second digital-to-analog converter havings its input connected to the output of said time base counter carrying said digital time signal; and

,

a X-Y display means having one of its X-Y control inputsconnected to the output of said first digital-to-analog converter and the other of its X-Y control inputs connected to the output of said second digital-to-analog converter and having its image control input connected to the output of said decision change detector.

10. A waveform digitizer as claimed in claim 7 including a frame controller connected to the said amplitude counter so as to receive a signal when said amplitude counter counts up to a predetermined value and in accordance therewith reset said amplitude counter and inhibit said hold off trigger circuit.