Hermetic plastic dual-in-line package for a semiconductor integrated circuit

• US 4,298,769 A
• Filed: 01/28/1981
• Issued: 11/03/1981
• Est. Priority Date: 12/14/1979
• Status: Expired due to Term

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Richman, Paul
• Primary Examiner(s): Reynolds, Bruce A.
• Assistant Examiner(s): TONE, DAVID
• Application Number:
  US06/229,193
• Time in Patent Office: 279 Days
• Field of Search: 174/52 FP, 174/52 PE, 357/72, 357/73, 357/74, 29/588, 29/589
• US Class Current: 174/50.51
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 Monolayer substrate
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: Y10T 29/49121 Beam lead frame or beam lead device

Abstract

A hermetic plastic package for a semiconductor integrated circuit chip includes a chip carrier provided with a plurality of conducting fingers that terminate at its underside. The carrier includes a pedestal onto which a semiconductor chip is bonded and wires are connected between the bonding pads on the chip and associated fingers on the carrier. A lid is placed over the carrier and is hermetically sealed with the chip inside the cavity of the carrier. The finger terminations on the underside of the carrier are connected to a plurality of leads which have inner portions that extend outward in a direction parallel to the underside of the carrier and end portions that are bent substantially perpendicular to the underside of the carrier configuration. The chip carrier and the inner portions of the leads that lie parallel to the underside of the chip carrier are encased in a plastic or epoxy compound.

Claims

1. A hermetic package for a semiconductor chip, said package comprising a ceramic chip carrier including a recessed portion having a bottom surface and at least one raised surface surrounding said recessed portion, a plurality of spaced conducting fingers arranged on said raised surface and extending to and terminating at the bottom surface of said chip carrier, a semiconductor chip in said recessed portion and including a plurality of bonding locations thereon, a corresponding plurality of bonding wires connected between said bonding locations and selected ones of said conducting fingers, a lid covering said carrier and sealing said chip within said carrier, and a lead frame separate from said chip carrier and having a significantly larger surface area than that of said chip carrier, said lead frame including a plurality of substantially rigid but bendable space leads constituting a free-standing assembly, each of said leads including spaced inner ends extending inwardly toward and terminating at a central portion of said lead frame to define the periphery of a central opening in said lead frame, said chip carrier being mounted to said lead frame over said central opening and being supported by said inner ends of said leads, said inner ends of said leads also being electrically connected to said conducting fingers at the bottom surface of said chip carrier, each of said leads further including an angular intermediate portion integral with and projecting away from said inner end and an outer portion integral with said intermediate portion and bent downward from said intermediate portion in a direction substantially perpendicular to said intermediate portion, said outer portions of said leads being spaced and substantially parallel to one another and defining the external connections for the package.

2. The package of claim 1, further comprising a seal ring attached to said carrier and arranged intermediate said carrier and said lid.

3. The hermetic package of claim 1, further comprising an encapsulating material encasing said chip carrier and at least a portion of said leads.

4. The package of claim 1, in which said carrier comprises a first raised surface surrounding said recessed portion and a second rasied surface surrounding said first raised surface and at a higher level as compared to said first raised surface.

5. The package of claim 4, in which said conducting fingers are formed on the upper surface of said first raised surface, and further comprising a seal ring attached to the upper part of said second raised surface and arranged intermediate said second raised surface and said lid.

6. A method of fabricating a package in which a semiconductor chip is hermetically sealed, said method comprising the steps of providing a free-standing lead frame including a plurality of integral, substantially rigid but bendable metal leads having inner and outer segments initially arranged in a common plane and interconnected at their outer ends by a conducting strip and terminating at their spaced inner ends at the periphery of a central opening;

providing a ceramic chip carrier separate from said lead frame and having a planar surface area significantly less than that of said lead frame, said carrier having a pedestal surrounded by at least one raised wall on which a plurality of spaced conducting fingers are provided and a bottom surface, said conducting fingers extending to and terminating at said bottom surface of said carrier;

mounting said chip carrier onto said spaced inner ends of said leads at said central opening of said lead frame and physically supporting said chip carrier on the rigid inner ends of said leads;

respectively electrically connecting said end portions of said conducting fingers on said chip carrier to said inner ends of said leads at said central opening;

placing a semiconductor chip having bonding locations onto said pedestal in said chip carrier;

connecting a plurality of wires between said bonding locations and selected ones of said conducting fingers on said raised wall of said chip carrier;

placing a lid over said pedestal and said chip, thereby hermetically sealing said chip in said chip carrier;

removing said conducting strip from said lead frame, thereby separating and electrically isolating said leads from one another;

bending the outer segments of said leads downwardly along a line intermediate said inner and outer parts so that said outer parts of said leads are substantially perpendicular to said inner parts; and

encapsulating said hermetically sealed chip carrier and said inner segments of said leads in a non-conductive material.