Non-interlaced to interlaced format video converter

• US 4,298,888 A
• Filed: 06/08/1979
• Issued: 11/03/1981
• Est. Priority Date: 06/08/1979
• Status: Expired due to Term

• Current Assignee: Palomar Technologies Incorporated
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Colles, Joseph H., Cooper, James E. Jr.
• Primary Examiner(s): ORSINO JR, JOSEPH
• Application Number:
  US06/046,745
• Time in Patent Office: 879 Days
• Field of Search: 358/134, 358/140, 360/8-11
• US Class Current: 348/446
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229

Abstract

A video converter operating in real time that responds to frames of N lines of video data in a non-interlaced format to form two fields of interlaced data without loss of any information. The converter operates with a minimum of two lines of memory storage capacity and a minimum of timing structure. The concept in accordance with the invention allows data of substantially any non-interlaced format to be converted for display on an interlaced display unit such as a standard TV system.

Claims

1. A video converter responsive to first and second frames of non-interlaced odd and even lines of input data received during first and second non-interlaced frame periods comprising:

first and second memory means each storing a line of input data,

a source of fast clock signals and slow clock signals coupled to said first and second memory means for being alternately applied to respective first and second memory means and to respective second and first memory means, alternating after each sequential pair of line periods of said input data, and

control means coupled to said first and second memory means for controlling said memory means to alternately write one line of input data in one memory means at the rate of said fast clock signals while reading one line of input data from the other memory means at the rate of said slow clock signals during first and second interlaced output field periods respectively occuring during said first and second non-interlaced frame periods, said control means including means to control said first and second memory means to write and read said odd lines of said input data during said first non-interlaced frame periods and to write and read said even lines of input data during said second non-interlaced frame periods.

2. A system for converting first and second frame of input data of a plurality of odd and even lines of a non-interlaced format to output data of first and second fields of an interlaced line format comprising:

first and second memory means each having the capacity for storing a line of input data and each having addressing means,

a source of fast clock and slow clock signals, multiplexing means coupled between said source and said addressing means of said first and second memory means for alternately applying the fast and slow clock signals to respective first and second memory means and to respective second and first memory means, alternating at the end of each sequential pair of input line periods, and

a source of control signals coupled to said first and second memory means for alternately controlling one memory means to read a line of output data while being addressed in response to the slow clock signals, and controlling the other memory means to write a line of input data in response to said fast clock signals, said source of control signals including field select means for controlling said memory means to read out a first field of odd lines of output data during reception of a first frame of input data and to read out a second field of even lines of output data during reception of a second frame of input data.

3. The combination of claim 2 in which said source of fast clock signals and slow clock signals includes means to provide said slow clock signals at a frequency that is one half of the frequency of said fast clock signals.

4. The combination of claim 2 in which said memory means is a random access memory and in which the addressing means of said first and second memory means are each a counter forming addresses in response to said fast or said slow clock signals.

5. The combination of claim 3 in which said source of control signals includes means to apply clear signals to said addressing means at the end of reading each line of output data.

6. The combination of claim 5 further including first and second gating means respectively coupled to outputs of said first and second memory means, and in which said source of control signals includes means to apply first and second gating signals to said first and second gating means to pass data to an output from the memory means from which data is being read and to inhibit signals from passing to said output from the memory means into which data is being written.

7. A system responsive to first and second input frames of odd and even lines of input data received from an input source during respective first and second input frame periods, each input frame having a noninterlaced line format, said system converting said first and second input frames to an output frame of respective odd and even fields of output data having an interlaced format comprising:

first and second random access memories each having capacity for storing a line of input data, said first and second random access memories being responsive to said first and second input frames during first and second input frame periods,

first and second counters respectively coupled to said first and second memories for sequentially addressing storage cells therein,

a timing source coupled to said first and second counters for providing fast and slow clock signals thereto, said fast clock signals having pulses synchronized with a pixel rate of said input data and said slow clock signals having pulses synchronized with a pixel rate of said output data, said timing source providing write mode and read mode signals, said timing source including means to change the phase of the write mode and read mode signals so that odd and even fields are read from said memories during respective first and second input frame periods,

multiplexing means coupled between said timing source and said first and second counters for alternately applying said fast and slow clock signals to said respective first and second counters and to said respective second and first counters, alternating each sequential second input line period, said multiplexing means being coupled to said first and second memories for alternately applying said write mode and said read mode signals to said respective first and second memories and to said respective second and first memories respectively in correspondence with said fast and slow clock signals applied to said first and second counters, and

output means coupled to said first and second memories for receiving said odd and even fields of said lines of data in an interlaced format at the rate of said slow clock signals.

8. The combination of claim 7 in which said input source provides a vertical synchronizing signal and said timing source includes field select means responsive to said vertical synchronizing signal to change the phase of said write mode and read mode signals.

9. The combination of claim 8 in which said timing source provides first and second clear signals which are respectively applied to said first and second counters for clearing the counter addressing said memory receiving write mode signals at the end of each input line time and clearing the counter receiving read mode signals at the end of each second input line time, and said field select means includes means to change the phase of said first and second clear signals during alternate input frame periods.

10. The combination of claim 9 in which said timing source includes means to provide said slow clock signals at a rate that is one half of the rate of said fast clock signals.

11. The combination of claim 10 in which said output means includes interlaced display means.