Non-interlaced to interlaced format video converter
First Claim
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1. A video converter responsive to first and second frames of non-interlaced odd and even lines of input data received during first and second non-interlaced frame periods comprising:
- first and second memory means each storing a line of input data,a source of fast clock signals and slow clock signals coupled to said first and second memory means for being alternately applied to respective first and second memory means and to respective second and first memory means, alternating after each sequential pair of line periods of said input data, andcontrol means coupled to said first and second memory means for controlling said memory means to alternately write one line of input data in one memory means at the rate of said fast clock signals while reading one line of input data from the other memory means at the rate of said slow clock signals during first and second interlaced output field periods respectively occuring during said first and second non-interlaced frame periods, said control means including means to control said first and second memory means to write and read said odd lines of said input data during said first non-interlaced frame periods and to write and read said even lines of input data during said second non-interlaced frame periods.
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Abstract
A video converter operating in real time that responds to frames of N lines of video data in a non-interlaced format to form two fields of interlaced data without loss of any information. The converter operates with a minimum of two lines of memory storage capacity and a minimum of timing structure. The concept in accordance with the invention allows data of substantially any non-interlaced format to be converted for display on an interlaced display unit such as a standard TV system.
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Citations
11 Claims
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1. A video converter responsive to first and second frames of non-interlaced odd and even lines of input data received during first and second non-interlaced frame periods comprising:
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first and second memory means each storing a line of input data, a source of fast clock signals and slow clock signals coupled to said first and second memory means for being alternately applied to respective first and second memory means and to respective second and first memory means, alternating after each sequential pair of line periods of said input data, and control means coupled to said first and second memory means for controlling said memory means to alternately write one line of input data in one memory means at the rate of said fast clock signals while reading one line of input data from the other memory means at the rate of said slow clock signals during first and second interlaced output field periods respectively occuring during said first and second non-interlaced frame periods, said control means including means to control said first and second memory means to write and read said odd lines of said input data during said first non-interlaced frame periods and to write and read said even lines of input data during said second non-interlaced frame periods.
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2. A system for converting first and second frame of input data of a plurality of odd and even lines of a non-interlaced format to output data of first and second fields of an interlaced line format comprising:
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first and second memory means each having the capacity for storing a line of input data and each having addressing means, a source of fast clock and slow clock signals, multiplexing means coupled between said source and said addressing means of said first and second memory means for alternately applying the fast and slow clock signals to respective first and second memory means and to respective second and first memory means, alternating at the end of each sequential pair of input line periods, and a source of control signals coupled to said first and second memory means for alternately controlling one memory means to read a line of output data while being addressed in response to the slow clock signals, and controlling the other memory means to write a line of input data in response to said fast clock signals, said source of control signals including field select means for controlling said memory means to read out a first field of odd lines of output data during reception of a first frame of input data and to read out a second field of even lines of output data during reception of a second frame of input data. - View Dependent Claims (3, 4, 5, 6)
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7. A system responsive to first and second input frames of odd and even lines of input data received from an input source during respective first and second input frame periods, each input frame having a noninterlaced line format, said system converting said first and second input frames to an output frame of respective odd and even fields of output data having an interlaced format comprising:
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first and second random access memories each having capacity for storing a line of input data, said first and second random access memories being responsive to said first and second input frames during first and second input frame periods, first and second counters respectively coupled to said first and second memories for sequentially addressing storage cells therein, a timing source coupled to said first and second counters for providing fast and slow clock signals thereto, said fast clock signals having pulses synchronized with a pixel rate of said input data and said slow clock signals having pulses synchronized with a pixel rate of said output data, said timing source providing write mode and read mode signals, said timing source including means to change the phase of the write mode and read mode signals so that odd and even fields are read from said memories during respective first and second input frame periods, multiplexing means coupled between said timing source and said first and second counters for alternately applying said fast and slow clock signals to said respective first and second counters and to said respective second and first counters, alternating each sequential second input line period, said multiplexing means being coupled to said first and second memories for alternately applying said write mode and said read mode signals to said respective first and second memories and to said respective second and first memories respectively in correspondence with said fast and slow clock signals applied to said first and second counters, and output means coupled to said first and second memories for receiving said odd and even fields of said lines of data in an interlaced format at the rate of said slow clock signals. - View Dependent Claims (8, 9, 10, 11)
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Specification