Synchronization circuit for video clock oscillators

• US 4,298,889 A
• Filed: 03/05/1980
• Issued: 11/03/1981
• Est. Priority Date: 03/16/1979
• Status: Expired due to Term

• Current Assignee: Siemens-Alris AG (Siemens AG)
• Original Assignee: Siemens-Alris AG (Siemens AG)
• Inventors: Tschannen, Gottfried, Burianek, Rudolf
• Primary Examiner(s): Masinick, Michael A.
• Application Number:
  US06/127,454
• Time in Patent Office: 608 Days
• Field of Search: 358/148, 358/149, 358/150, 358/151, 358/152, 358/153, 358/154, 358/210
• US Class Current: 348/512
• CPC Class Codes: H04N 5/06 Generation of synchronising signals

Abstract

A synchronization circuit for video clock generators, wherein in order to obtain a line synchronization simultaneous with a complete image synchronization, there is provided a follow-up control which delivers a clock frequency signal. The follow-up control has its reference input connected with the output of a line pulse-separation circuit, delivering an external horizontal pulse signal, and is further connected with the input of an external complete image characteristic or marker pulse-separation circuit. Both of the separation circuits have infed at their input side a mixed pulse signal. The external complete image-characteristic pulse-separation circuit is connected at its output side with the first input of a comparator, the second input of which has infed thereto the output signal of an internal complete image characteristic pulse-separation circuit. The output signal of the comparator is infed to the first input of a regulation pulse-switch means, whose output is connected with the clock input of a clock generator, delivering to a respective output an internal mixed pulse signal and an internal horizontal pulse signal. The latter is delivered to the comparator input of the follow-up control and the first input of the internal complete image-characteristic pulse-separation circuit, the second input of which receives the internal mixed pulse signal. The output of the follow-up control is connected with the second input of the regulation pulse switch means.

Claims

1. A synchronization circuit for video clock generators, in order to obtain a line synchronization simultaneous with a complete image synchronization, comprising:

a follow-up control having an output and delivering a clock frequency signal;

said follow-up control having a reference input and a comparison input;

a line pulse separation circuit having an output delivering an external horizontal pulse signal;

said follow-up control having said reference input connected with said output of the line pulse-separation circuit which delivers said external horizontal pulse signal;

an external complete image-characteristic pulse-separation circuit having an input and an output;

the reference input of the follow-up control being connected with the input of the external complete image-characteristic pulse-separation circuit;

both of the separation circuits being impinged at their input sides with a mixed pulse signal;

a comparator having a first input and a second input and delivering an output signal;

the external complete image-characteristic pulse-separation circuit being connected at its output with the first input of the comparator;

an internal complete image-characteristic pulse-separation circuit having a first input and a second input and delivering an output signal;

the second input of the comparator receiving the output signal of the internal complete image-characteristic pulse-separation circuit;

a regulation pulse-switch means having a first input and a second input;

the output signal of the comparator being infed to the first input of the regulation pulse-switch means;

said regulation pulse-switch means having an output;

a video clock generator having a clock input;

the output of the regulation pulse-switch means being connected with the clock input of said video clock generator;

said video clock generator having respective outputs delivering respectively an internal mixed pulse signal and an internal horizontal pulse signal;

said internal horizontal pulse signal being infed to the comparison input of the follow-up control and the first input of the internal complete image-characteristic pulse-separation circuit;

said internal complete image-characteristic pulse-separation circuit receiving at its second input the internal mixed pulse signal; and

said follow-up control having its output connected with the second input of the regulation pulse-switch means.

2. The synchronization circuit as defined in claim 1, further including:

an external-internal switch means for connecting the follow-up control with the second input of the regulation pulse-switch means such that the output of the follow-up control is connected with a first input of the external-internal switch means;

a clock pulse source delivering an output signal;

said external-internal switch means having a second input which receives the output signal of said clock pulse source;

an external-internal control means having an output;

said regulation pulse-switch means having a third input which is connected with a control input of the external-internal switch means and with the output of said external-internal control means which detects the presence of a mixed pulse signal at the input of the synchronization circuit.

3. The synchronization circuit as defined in claim 2, further including:

at least one clock divider incorporated between the output of the external-internal switch means and the input of the video clock generator.

4. The synchronization circuit as defined in claim 3, wherein:

the video clock generator comprises a TV clock generator having a horizontal pulse signal output and a mixed pulse signal output;

a first D-flipflop having a D-input;

a second D-flipflop having a D-input; and

the horizontal pulse signal output of the TV-clock generator being connected with the D-input of the first D-flipflop and the mixed pulse signal output being connected with the D-input of the second D-flipflop.

5. The synchronization circuit as defined in claim 4, further including:

a line pulse-reversing switch means having a first input and a second input;

the external horizontal pulse signal being infed to the first input of said line pulse-reversing switch means;

said line pulse-reversing switch means having a control input receiving the output signal of the comparator;

the comparison input of the follow-up control having infed thereto the internal horizontal pulse signal by means of the second input of the line pulse-reversing switch means.

6. The synchronization circuit as defined in claim 5, wherein:

said line pulse-reversing switch means comprises two AND-gates whose outputs are linked together by means of an OR-gate;

an input of one of said AND-gates, constituting a first control input of the line pulse-reversing switch means, receiving a non-inverted output signal of the comparator and an input of the other AND-gate, serving as the second control input of the line pulse-reversing switch means, receiving the inverted output signal of the comparator.

7. The synchronization circuit as defined in claim 1, wherein:

said follow-up control comprises a phase-comparator having an input side and an output side;

said input side of the phase comparator being connected with the output of a first monoflop and with the output of a second monoflop; and

the output side of the phase comparator delivering the clock frequency signal by means of a series circuit of an integrator circuit, an oscillator circuit, a high-pass filter and an output-amplifier circuit.

8. The synchronization circuit as defined in claim 7, wherein:

said integrator has an output;

a reference voltage source; and

a Zener-diode connecting the output of the integrator with the reference voltage source.

9. The synchronization circuit as defined in claim 1, wherein:

said line pulse-separation circuit comprises a first monoflop having a clock input which is impinged with the mixed pulse signal and delivering an output signal;

a NAND-gate having a first input, a second input and an output;

the output signal of the first monoflop being delivered to the first input of the NAND-gate;

an inverter having an input and an output;

a second monoflop having a clock input;

the output of the NAND-gate being connected with the input of the inverter and with the clock input of the second monoflop;

said second monoflop delivering an inverted output signal to the second input of the NAND-gate; and

said inverter delivering at its output the horizontal pulse signal.

10. The synchronization circuit as defined in claim 1, wherein:

said external complete image-characteristic pulse-separation circuit comprises a first monoflop and a second monoflop;

said first monoflop being impinged by a clock input with the mixed pulse signal;

said second monoflop being impinged by a clock input with the output pulse signal of a D-flipflop;

said D-flipflop having infed by means of its D-input the mixed pulse signal and by means of its clock input the inverted output pulse signal of the first monoflop;

said external complete image-characteristic pulse-separation circuit having a NAND-gate;

said NAND-gate having a first input impinged with the horizontal pulse signal and a second input impinged with the output pulse signal of the second monoflop and whose output pulse signal constitutes the external complete image-characteristic pulse.