Decoding TIM bus structure
First Claim
1. In a demand assignment communications system having a plurality of stations, each of said stations transmitting a burst of data at a selected time, each burst having a plurality of channel portions, each station receiving selected channel portions of selected bursts of data, an apparatus for selecting said channel portions of said selected bursts of data comprising:
- (a) means for counting said channel portions of data for providing a portion count output;
(b) means having an input/output function receiving said portion count output for providing a selection signal in accordance with said input/output function;
said selection signal thereby selecting said selected channel portion;
(c) means for changing said input/output function so as to change the selected channel portion in accordance with said input/output changing means;
wherein said means having said input/output function comprises a pair of memory means; and
said means for changing said input/output function comprises;
a central processing unit (CPU);
first and second multiplexers controlled by said CPU selectively providing an address from said CPU to one of said memory means, the other of said memory means receiving said portion count output;
a third multiplexer controlled by said CPU selectively delivering data from said CPU to said one of said memory means; and
a fourth multiplexer controlled by said CPU selectively delivering said selection signal from said other of said memory means, wherein said selected channel portion may be changed in real time.
1 Assignment
0 Petitions
Accused Products
Abstract
A multiplexing/demultiplexing bus structure for a TDMA communications system employs a mapping RAM in common equipment and a decoding device in a plurality of interface modules. The common equipment provides identical encoded information to each of the decoders in the interface modules, the decoders in each of the interface modules determining whether or not incoming or outgoing data is to be written into or read from the associated interface module. The decoders initiate a count to provide an address for the data written into or read out of a buffer in the associated interface module. The common equipment can thereby provide burst-to-burst selection of data. Burst and/or channel allocation may be changed in real time for any of the interface modules through a "demand assignment" process. A central network controller receives all capacity and destination requests for processing. The controller can then send capacity and destination assignments to network stations where they are received and decoded. The mapping functions of the appropriate RAMs are updated in accordance with the central network controller'"'"'s instructions.
33 Citations
8 Claims
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1. In a demand assignment communications system having a plurality of stations, each of said stations transmitting a burst of data at a selected time, each burst having a plurality of channel portions, each station receiving selected channel portions of selected bursts of data, an apparatus for selecting said channel portions of said selected bursts of data comprising:
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(a) means for counting said channel portions of data for providing a portion count output; (b) means having an input/output function receiving said portion count output for providing a selection signal in accordance with said input/output function;
said selection signal thereby selecting said selected channel portion;(c) means for changing said input/output function so as to change the selected channel portion in accordance with said input/output changing means; wherein said means having said input/output function comprises a pair of memory means; and
said means for changing said input/output function comprises;a central processing unit (CPU); first and second multiplexers controlled by said CPU selectively providing an address from said CPU to one of said memory means, the other of said memory means receiving said portion count output; a third multiplexer controlled by said CPU selectively delivering data from said CPU to said one of said memory means; and a fourth multiplexer controlled by said CPU selectively delivering said selection signal from said other of said memory means, wherein said selected channel portion may be changed in real time.
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2. In a data communications system having a plurality of stations, each of said stations transmitting a burst of data at a selected time, each burst having a plurality of channel portions, each station receiving selected channel portions of selected bursts of data, an apparatus for allocating said selected channel portions of selected bursts to said stations comprising:
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(a) means for counting and tracking said bursts of data to provide an initialization signal; (b) means receiving said initialization signal and a clock signal for counting said channel portions of data and for providing a portion count output; (c) means receiving said portion count output for providing a selection signal; (d) wherein said means for counting said channel portions is preset in accordance with said initialization signal, said presetting occurring for each new burst of data. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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Specification