Apparatus for processing digital data representative of a two-dimensional image

• US 4,300,122 A
• Filed: 04/02/1979
• Issued: 11/10/1981
• Est. Priority Date: 04/02/1979
• Status: Expired due to Term

• Current Assignee: Sperry Corporation (Unisys Corporation)
• Original Assignee: Sperry Corporation (Unisys Corporation)
• Inventors: McMahon, Donald H.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/025,702
• Time in Patent Office: 953 Days
• Field of Search: 340/146.3 H, 340/146.3 MA, 340/146.3 R, 340/146.3 AC, 364/488, 364/489, 364/490, 364/491, 364/515, 358/106, 250/363 S
• US Class Current: 382/147
• CPC Class Codes: G06V 10/443 by matching or filtering

Abstract

An apparatus for processing binary data in line sequential format indicative of the presence of selected features in a two-dimensional binary data point array generates corner codes which classify the nature of such selected features. In one embodiment of the apparatus, means are provided for producing data matrices representative of the states of adjacent binary image points in the array; a corner code generator is coupled with the matrix means for producing the corner codes by analyzing the contents of each data matrix.

Claims

1. An apparatus for converting binary data representative of data squares in a two dimensional array to a corner code data format, comprising:

coding means coupled to receive said binary data for providing a multiplicity of corner codes each indicative of one corner feature of a multiplicity of corner features in said two dimensional array, said corner features defined in complementary pairs; and

excess code elimination means coupled to receive said corner code data for eliminating corner codes corresponding to horizontally adjacent and vertically adjacent complementary corner features and for providing at an output means remaining corner codes.

2. An apparatus as recited in claim 1 wherein said complementary corner features have values selected to sum to a predetermined elimination code;

and

wherein said excess code elimination means eliminates vertically adjacent and horizontally adjacent corner code data whose values sum to said predetermined elimination code.

3. An apparatus as recited in claim 2 wherein said coding means comprises:

first matrix means having an input terminal coupled to receive said binary data for providing data matrices with elements that are representative of adjacent binary data in said two dimensional array; and

corner code generator means coupled to receive said data matrices for producing said corner codes, each of said corner codes being indicative of a corner feature in said two dimensional array.

4. An apparatus as recited in claim 3 wherein said corner code generator means comprises an ROM.

5. An apparatus as recited in claim 3 wherein said first matrix means comprises:

first line shift register means coupled to said input terminal of said first matrix means and having an output terminal coupled to said corner code generator means for providing to said corner code generator means a data bit in said array vertically adjacent to a data bit of said array most recently entered to said first matrix means;

first single shift register means coupled to said input terminal of said first matrix means and having an output terminal coupled to said corner code generator means for providing to said corner code generator means a data bit in said array horizontally adjacent to said data bit of said array most recently entered to said first matrix means; and

second single shift register means coupled to said output terminal of said first line shift register means and having an output terminal coupled to said corner code generator means for providing to said corner code generator means a data bit in said array vertically adjacent to said data bit of said array provided at said output terminal of said first single shift register means and horizontally adjacent to said data bit of said array provided at said output terminal of said first line shift register means.

6. An apparatus as recited in claim 2 wherein said corner codes have assigned values ranging from zero (0) through seven (7) and said predetermined elimination code equals seven (7).

7. The apparatus of claim 3, wherein said matrix means is operative to provide 2×

2 data matrices at its matrix output.

8. The apparatus of claim 2 wherein said coding means is operative to produce an enable signal indicative of the presence of a corner feature, said enable signal being provided to said elimination means along with said corner code;

and said elimination means is operative to eliminate those enable signals corresponding to horizontally and vertically adjacent groups of data whose corner code values sum to said predetermined elimination code.

9. The apparatus of claim 1 further comprising smoothing means coupled to receive said binary data for producing a smoothed binary signal for a first data square, said smoothed signal having a value equal to a first binary state when the number of data squares having said first binary number in a group of data squares, including said first data square and data squares adjacent thereto, is equal or greater than a preselected total, and equal to a second binary state when the number of said data squares in said group is less than said preselected total, said smoothed signal being provided to said input terminal of said coding means.

10. The apparatus of claim 9, wherein said number of data squares in said group is equal to nine and said preselected total is equal to four.

11. The apparatus of claim 9, wherein said number of data squares in said group is equal to nine and said preselected total is equal to five.

12. An apparatus as recited in claim 9 wherein said smoothing means comprises:

second matrix means having an input terminal coupled to receive said binary data for providing data matrices with elements that are representative of adjacent binary data in said two dimensional array; and

means coupled to receive said data matrices for reassigning binary signals for said first data square, said reassigned binary signals being coupled to said coding means.

13. An apparatus as recited in claim 12 wherein said second matrix means comprises:

second line shift register means coupled to said input terminal of said second matrix means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array vertically adjacent to a data bit of said array most recently entered to said second matrix means;

third line shift register means coupled to said output terminal of said second line shift register means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array vertically adjacent to said data bit of said array provided at said output terminal of said second line shift register means;

third single shift register means coupled to said input terminal of said second matrix means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array horizontally adjacent to said data bit of said array most recently entered to said second matrix means;

fourth single shift register means coupled to said output terminal of said third single shift register means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array horizontally adjacent to said data bit of said array provided at said output terminal of said third single shift register means;

fifth single shift register means coupled to said output terminal of said second line shift register means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array vertically adjacent to said data bit of said array provided at said output terminal of said third single shift register means and horizontally adjacent to said data bit of said array provided at said output terminal of said second line shift register means;

sixth single shift register means coupled to said output terminal of said fifth single shift register means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array vertically adjacent to said data bit of said array provided at said output terminal of said fourth single shift register means and horizontally adjacent to said data bit of said array provided at said output terminal of said fifth single shift register means;

seventh single shift register means coupled to said output terminal of said third line shift register means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array vertically adjacent to said data bit of said array provided at said output terminal of said fifth single shift register means and horizontally adjacent to said data bit of said array provided at said output terminal of said third line shift register means; and

eighth single shift register means coupled to said output terminal of said seventh single shift register means and having an output terminal coupled to said binary signal reassigning means for providing to said binary signal reassigning means a data bit in said array vertically adjacent to said data bit of said array provided at said output terminal of said sixth single shift register means and horizontally adjacent to said data bit of said array provided at said output terminal of said seventh single shift register means.

14. An apparatus as recited in claim 13 wherein said binary signal reassigning means comprises a read only memory (ROM).