Lateral double-diffused MOS transistor device

• US 4,300,150 A
• Filed: 06/16/1980
• Issued: 11/10/1981
• Est. Priority Date: 06/16/1980
• Status: Expired due to Term

• Current Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Colak, Sel
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US06/159,883
• Time in Patent Office: 512 Days
• Field of Search: 357/23, 357/52, 357/13
• US Class Current: 257/336
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: Y10S 257/901 MOSFET substrate bias

Abstract

A lateral double-diffused MOS transistor includes a field-shaping semiconductor layer which serves to improve the breakdown voltage and/or on-resistance characteristics of the device. The field-shaping layer redistributes the electrical field in the device during operation in order to eliminate electrical field crowding in portions of the device where breakdown would otherwise first occur. The field shaping layer may be a buried layer, a surface layer, or a composite layer having both buried and surface layer portions.

Claims

1. A lateral double-diffused MOS transistor having a semiconductor substrate of a first conductivity type, an epitaxial surface layer of a second conductivity type opposite to that of the first on a major surface of said substrate, a surface-adjoining channel region of said first conductivity type in said epitaxial layer and forming a p-n junction therewith, a surface-adjoining source region of said second conductivity type in said channel region, a surface-adjoining drain region of said second conductivity type in said epitaxial layer and spaced apart from said channel region, an insulating layer on said surface layer and covering at least that portion of said channel region located between said source region and said drain region, a gate electrode on said insulating layer, over said portion of the channel region and electrically isolated from said surface layer, and source and drain electrodes connected respectively to the source and drain regions of said transistor, characterized in that an electrical field redistribution means comprising a field-shaping semiconductor layer of said first conductivity type and having a doping level greater than that of said substrate is provided adjacent but spaced apart from said channel region for reducing the electrical field density during operation in a first part of the epitaxial layer mainly located adjacent said p-n junction and between said source and drain regions while increasing the electrical field density during operation in a second part of the epitaxial layer mainly located adjacent said drain region.

2. A lateral double-diffused transistor as in claim 1, wherein the doping concentration and thickness of said epitaxial surface layer are selected in accordance with the REduced SURface Field ((RESURF) technique.

3. A lateral double-diffused transistor as in claim 1 or 2, wherein said field-shaping semiconductor layer is a buried layer provided substantially in said substrate at said major surface thereof and extends at least beneath said channel region and said first part of the epitaxial layer.

4. A lateral double-diffused transistor as in claim 3, wherein said buried layer has a thickness of about 3.0 to 5.0 micrometers and a doping level of about 1.0 to 1.5×

10¹² atoms/cm², and said epitaxial layer has a thickness of about 6.0 micrometers and a doping level of about 3.0×

10¹⁵ atoms/cm³.

5. A lateral double-diffused transistor as in claim 1 or 2, wherein said field-shaping semiconductor layer is a surface layer provided in a surface-adjoining region of said epitaxial layer alongside said drain region and extending from said drain region toward, but not contacting, said channel region.

6. A lateral double-diffused transistor as in claim 5, wherein said surface layer has a thickness of about 1.0 to 1.5 micrometers and a doping level of about 1.0×

10¹² atoms/cm², and said epitaxial layer has a thickness of about 6.0 micrometers and a doping level of about 3.0×

10¹⁵ atoms/cm³.

7. A lateral double-diffused transistor as in claim 1 or 2, wherein said field-shaping semiconductor layer comprises a buried layer portion provided substantially in said substrate at said major surface and extending at least beneath said channel region and said first part of the epitaxial layer, and a surface layer portion provided in a surface-adjoining region of said epitaxial layer alongside said drain region and extending from said drain region toward, but not contacting, said channel region.

8. A lateral double-diffused transistor as in claim 7, wherein said buried layer portion has a thickness of about 3.0 to 5.0 micrometers and a doping level of about 0.5 to 0.75×

10¹² atoms/cm², said surface layer portion has a thickness of about 1.0 to 1.5 micrometers and a doping level of about 0.5×

10¹² atoms/cm², and said epitaxial layer has a thickness of about 6.0 micrometers and a doping level of about 3.0×

10¹⁵ atoms/cm³.