Nonvolatile static random access memory devices

• US 4,300,212 A
• Filed: 01/24/1979
• Issued: 11/10/1981
• Est. Priority Date: 01/24/1979
• Status: Expired due to Term

• Current Assignee: Xicor LLC (Renesas Electronics Corporation)
• Original Assignee: Xicor LLC (Renesas Electronics Corporation)
• Inventors: Simko, Richard T.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/006,029
• Time in Patent Office: 1,021 Days
• Field of Search: 365/51, 365/174, 365/185, 357/23, 357/24
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents.

Claims

1. A nonvolatile memory device comprising a volatile semiconductor memory cell for storing binary data, means for reading from and writing to said volatile memory cell, a nonvolatile memory means, comprising an electrically insulated floating gate conductor, for storing binary data as one of two different electric charge levels on said floating gate conductor, means for capacitively coupling said volatile memory cell to said nonvolatile memory means and for copying the memory state of said bistable memory cell to the floating gate conductor at a predetermined one of said electric charge levels, and means for capacitively coupling said floating gate conductor of said nonvolatile memory means to the said volatile memory cell for copying the memory state of said floating gate to said volatile memory cell upon application of electrical power to said volatile memory cell.

2. The cell of claim 1 in which the volatile memory cell is a bistable cross-coupled flip-flop memory cell.

3. The cell of claim 1 in which the memory cell is a six-transistor n-channel static random-access memory cell.

4. The cell of claim 1 in which the memory cell is a four-transistor n-channel static random-access memory cell.

5. A cell in accordance with claim 1 in which said memory cell is a six-transistor CMOS/SOS static random-access memory cell.

6. The cell of claim 1 in which said memory cell is a six-transistor bulk CMOS static random-access memory cell.

7. A cell in accordance with claim 1 wherein the nonvolatile memory means comprises a plurality of electrodes and wherein at least two of said electrodes and said floating gate are constructed with three layers of polysilicon.

8. A cell in accordance with claim 1 wherein asperities are provided to promote electron flow to and from said floating gate conductor component of said nonvolatile memory means.

9. A cell in accordance with claim 1 wherein said means for copying the memory state of said cell to said floating gate conductor includes an electrode positioned capacitively adjacent said floating gate conductor, such that application of a single "store" voltage control signal to said electrode causes the present memory state of said volatile memory cell to be transferred into said nonvolatile memory means.

10. A cell in accordance with claim 1 in integrated circuit array with a plurality of like cells.

12. The cell of claim 1 wherein said means for reading from and writing to said volatile memory cell comprises a single erase/store gate capacitively coupled to said floating gate conductor wherein a single positive polarity voltage enables both the charging and discharging of such floating gate conductor.

11. A method for nonvolatile storage of binary information in a semiconductor integrated circuit, comprising the steps of

capacitively sensing the one of two binary memory states of a volatile semiconductor memory cell having binary information stored therein,

causing a predetermined one to two electric charge levels to be created on a dielectrically isolated floating gate conductor corresponding to said one capacitively sensed memory state of said volatile memory cell without altering the memory state of said volatile memory cell, and

causing said volatile memory cell to capacitively sense the current charge level of said floating gate when power is first coupled to said volatile memory cell, such that the memory state of said volatile memory cell corresponds to said charge level of said floating gate.

13. A method in accordance with claim 11 wherein the step of providing a predetermined one of two electric charge levels on said floating gate conductor comprises the step of coupling a single positive polarity voltage to an erase/store gate capacitively coupled to said floating gate conductor.