Electronic overload protection circuit

• US 4,301,490 A
• Filed: 07/09/1979
• Issued: 11/17/1981
• Est. Priority Date: 07/09/1979
• Status: Expired due to Term

• Current Assignee: Union Switch & Signal, Inc. (Hitachi, Ltd.)
• Original Assignee: American Standard Inc. (Trane Technologies plc)
• Inventors: Kuhn, John J., Nagel, Harry C.
• Primary Examiner(s): Moose, Jr., Harry E.
• Application Number:
  US06/055,864
• Time in Patent Office: 862 Days
• Field of Search: 330/207 P, 330/298, 361/100, 361/89, 361/90, 361/91
• US Class Current: 361/89
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74

Abstract

A solid-state overload protection circuit for protecting a multiple-stage compound transistor power amplifier. The overload protection circuit includes a current-limiting circuit for sensing or limiting the current during an overload condition. The current-limiting circuit includes a transistor which conducts to limit the current in the output stages of the multiple-stage power amplifier. A monitoring circuit including a timing circuit, a comparator, and a switching transistor monitors the duration of the overload condition and disables the input stages of the multiple-stage power amplifier when a prolonged overload condition persists.

Claims

1. An electronic overload protection arrangement for a multiple-stage amplifying circuit comprising, a current-limiting circuit interconnected to the multiple-stage amplifying circuit for limiting the current during an overload condition, and a monitoring circuit connected with said current-limiting circuit and the multiple-stage amplifying circuit for monitoring the current-limiting action and for disabling the multiple-stage amplifying circuit when the duration of the current-limiting action exceeds a predetermined period of time.

2. The electronic overload protection arrangement as defined in claim 1, wherein said current-limiting circuit includes a transistor which is rendered conductive during the presence of an overload condition.

3. The electronic overload protection arrangement as defined in claim 1, wherein said monitoring circuit includes an R-C circuit for establishing the predetermined period of time.

4. The electronic overload protection arrangement as defined in claim 1, wherein said current-limiting circuit limits the current in a power output stage of the multiple-stage amplifying circuit.

5. The electronic overload protection arrangement as defined in claim 1, wherein said monitoring circuit includes a timing circuit, a comparator circuit, and a switching circuit for measuring the time duration of overload conditions by charging a capacitor, for comparing the potential charge on the capacitor with a reference voltage and for turning off said switching circuit when the potential charge exceeds the reference voltage.

6. The electronic overload protection arrangement as defined in claim 1, wherein said current-limiting circuit includes a pair of diodes and a transistor which conducts during an overload condition to limit the current flow in a pair of output power transistor stages.

7. The electronic overload protection arrangement as defined in claim 5, wherein said timing circuit includes a series resistance-capacitance circuit, a bleed-off resistor and a time-averaging circuit including a diode, resistor, and capacitor.

8. The electronic overload protection arrangement as defined in claim 5, wherein said comparator circuit includes an integrated circuit operational amplifier which toggles when the potential charge exceeds the reference voltage.

9. The electronic overload protection arrangement as defined in claim 5, wherein said switching circuit includes a transistor which interrupts the supply voltage to a pair of input transistor stages.

10. The electronic overload protection circuit as defined in claim 6, wherein a pair of snubbing diodes are connected to the output circuit of said pair of output power transistor stages for shunting voltage transients appearing across said output circuit.

11. The electronic overload protection arrangement as defined in claim 1, wherein said current-limiting circuit is interconnected between the intermediate and output stages of the multiple-stage amplifying circuit and said monitoring circuit is connected to the input stages of the multiple-stage amplifying circuit.

12. The electronic overload protection arrangement as defined in claim 6, wherein another pair of diodes are rendered conductive when said transistor saturates to limit the current flow in the base of said transistor.