Programmable controller using microprocessor

• US 4,303,990 A
• Filed: 01/02/1980
• Issued: 12/01/1981
• Est. Priority Date: 07/01/1976
• Status: Expired due to Term

• Current Assignee: Eagle Acquisition Corp. (Maxlinear Incorporated)
• Original Assignee: Gulf & Western Industries Incorporated
• Inventors: Seipp, William H.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): BARTZ, CLIFFORD T
• Application Number:
  US06/109,164
• Time in Patent Office: 699 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/267
• CPC Class Codes: G05B 19/05 Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
• CPC Class Codes: G05B 2219/1105 I-O
• CPC Class Codes: G05B 2219/13001 Interrupt handling
• CPC Class Codes: G05B 2219/14142 Low impedance bus
• CPC Class Codes: G05B 2219/15048 Microprocessor
• CPC Class Codes: G05B 2219/15056 DMA
• CPC Class Codes: G05B 2219/15105 Hardwired logic to accelerate, speed up execution of instructions
• CPC Class Codes: G05B 2219/15116 Pc implements plc, in application program, plc instruction register
• CPC Class Codes: G05B 2219/15122 Less frequent used subroutines arranged at high addresses
• CPC Class Codes: G05B 2219/15127 Bit and word, byte oriented instructions, boolean and arithmetic operations
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 15/7864 on more than one IC chip

Abstract

In a programmable controller of the type including a microprocessor having output address terminals, output address lines extending to external addressable devices, input/output bi-directional data terminals and means for applying a binary status code made up of binary signals on the data terminals at a preselected time during a cycle of the microprocessor and indicative of the type of machine cycle to be processed by the microprocessor there is provided a system for energizing a hardwired logic circuit in response to a status code and logic on said address lines.

Claims

1. In a programmable controller including a microprocessor having output address terminals connected to address lines extending to external addressable devices, input/output bi-directional data terminals connected to means in said microprocessor for applying a binary status code made up of binary signals on said data terminals at a preselected time during a cycle of said microprocessor and indicative of the type of machine cycle being processed by said microprocessor, the improvement comprising:

a system for energizing a hardwired logic circuit in response to a status code and logic on said address lines, said system including;

a logic decoder means for producing one of several selected output signals in response to a logic signal on at least one of said address terminals and a logic signal created by the status code on at least one of said data terminals at said preselected time;

said hardwired logic circuit being placed in a particular condition upon being energized; and

energizing means responsive to one of said selected output signals of said decoder means for energizing said hardwired logic circuit;

said logic decoder means including input terminals and output terminals, means for directing at least one of the address logic signals on said address terminals to selected ones of said input terminals of said decoder means, means for directing a status indicative logic signal determined by said status code at said preselected time to at least a different one of said input terminals of said decoder means, means responsive to said address logic signal and said status indicative signal for creating said output signal in one of said output terminals of said decoder means and means for connecting said one of said output terminals to said energizing means for said hardwired logic circuit for energizing said hardwired logic circuit.

2. The improvement as defined in claim 1 including means for holding a given signal on at least a selected one of said address lines in response to certain logic signals on said data terminals, said selected one of said address lines being different from the address lines connected to said input terminals of said decoder means and corresponding to a most significant address of an associated memory unit, and means for controlling the memory access position to said memory unit in response to said logic held on said selected one of said address lines.

3. The improvement as defined in claim 1 including a latch means for latching the status code logic signals of said data terminals at said preselected time at output terminals of said latch means and means for directing said latched status code logic signals of said output terminals of said latch means to selected ones of said input terminals of decoder means.

4. The improvement as defined in claim 3 wherein said latch means includes input terminals connected to said data terminals and receiving status code logic signals therefrom, means for shifting said logic signals of said data terminals from said input terminals of said latch means to said output terminals of said latch means in response to a synchronizing signal from said microprocessor and means for inhibiting said decoder means during said synchronizing pulse.

5. In a programmable controller including a microprocessor having output address terminals connected to address lines connectable to said address terminals, input/output bi-directional data terminals connected to means in said microprocessor for applying a binary status code made up of binary signals on said data terminals at a preselected time during a cycle of said microprocessor and indicative of the type of machine cycle to be processed by said microprocessor, the improvement comprising:

a system for shifting the state of a bi-stable device in response to said status code and logic on said address lines, said including;

a logic decoder means having input terminal means for receiving logic signals indicative of said status code on said data terminals and a logic signal from at least one of said address lines and output terminals for providing a first signal on a first output terminal of said decoder in response to a first pattern of logic signals directed to said decoder input terminal means from at least one of said address lines and said binary status code from at least one of said data terminals at a given cycle of said microprocessor and a second signal in a second output terminal in response to a second pattern of logic signals directed to said decoder input terminal means from said at least one of said address lines and said binary status code at another cycle of said microprocessor and at least at one data terminal, said bi-stable device having an output line shiftable between first and second output logic states;

means connecting said first output terminal to said device for shifting said bi-stable device into said first output state in said output line upon creation of said first signal and means connecting said second output terminal to said device for shifting said bi-stable device into said second output state in said output line upon creation of said second signal; and

, means for initiating a function of said controller in response to said first logic state in said output line.

6. In a programmable controller including a microprocessor having output address terminals connected to output address lines extending to external addressable devices, input/output bi-directional data terminals connected to means in said microprocessor for applying a binary logic status code made up of logic signals on said data terminals at a preselected time during a cycle of said microprocessor and indicative of the type of machine cycle to be processed by said microprocessor, the improvement comprising:

a system for creating a control signal in response to said status code and the signal on at least one of said address lines, said system including;

a decoder having input terminals and means for creating an output signal in selected ones of several output terminals in response to the logic pattern applied to said input terminals of said decoder, said output signal being used as a control signal for a binary signal controlled device external of said microprocessor;

data transfer means for selectively transferring the status code logic signal of at least one of said data terminals of said microprocessor at said preselected time to one of said input terminals of said decoder at a given time different from said preselected time; and

, address transfer means for transferring signals on at least one of said address lines to one of said input terminals of said decoder at least during said given time to create said control signal at said given time.

7. In a programmable controller including a microprocessor having output address terminals connected to address lines connectable to said address terminals, input/output bi-directional data terminals, and means in said microprocessor connected to the input/output bi-directional data terminals for applying a binary status code made up of binary signals to said data terminals during a particular type of machine cycle of said microprocessor and indicative of the type of machine cycle to be processed by said microprocessor, and means for latching connected to the input/output bi-directional data terminals, which latches said binary status code into a series of hardwired logic terminals at the output side of a data latch, the improvement comprising:

a logic circuit having input terminals and output terminals for creating one of a series of control signals in said output terminals in response to input logic signals at said input terminals;

means for connecting at least one of said hrdwired logic terminals to a selected one of said input terminals of said logic circuit; and

, means for selectively connecting at least one of said address lines to respective ones of said input terminals of said logic circuit, said respective ones of said input terminals of said logic circuit being different from said selected one of said input terminals of said logic circuit whereby the signal at the output terminals of said logic circuit is controlled by both the binary signals of said sttus code and the logic on at least one address line.