Data scrambler

• US 4,304,962 A
• Filed: 08/25/1965
• Issued: 12/08/1981
• Est. Priority Date: 08/25/1965
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Tammaru, Tarmo, Fracassi, Renato D.
• Primary Examiner(s): Birmiel, Howard A.
• Application Number:
  US04/482,498
• Time in Patent Office: 5,949 Days
• Field of Search: 178/22, 178/22.12, 178/22.19, 178/22.14, 325/324
• US Class Current: 380/42
• CPC Class Codes: H04L 25/03866 using scrambling

Abstract

Binary digital data signal patterns containing either no transitions, periodically recurring transitions or both are randomized by constructing a key signal from a summation of selected stored digits of the data pattern and combining such key signal with the data signal to form a scrambled line signal for transmission. The line signal so constructed is free of signal energy concentrated at particular frequencies and provides signal transitions adequate in number to assure reliable recovery of synchronization information. Descrambling of the received line signal is accomplished by precisely the inverse of the scrambling operation. The system is self-synchronizing because the key signals constructed by each of the scrambler and descrambler are derived from the same line signal.

Claims

1. Apparatus for scrambling and descrambling a nonrandom alternating binary data sequence during its passage through a transmission channel to spread the signal energy over the frequency bandwidth of said channel comprising

first means for storing successive data bits arranged in order of occurrence,

means for half-adding pairs of selected bits from said first storing means to form individual bits of a key signal,

further means for half-adding bits of said key signal to said data sequence to form a quasi-random line signal for application to said transmission channel and to said first storing means,

second means for storing successive bits of the line signal from said transmission channel arranged in order of occurrence,

means for half-adding pairs of selected bits from said second storing means to reconstitute the individual bits of said key signal, and

final means for half-adding bits of said key signal to said line signal to recover said data sequence.

2. Apparatus for scrambling and descrambling a continuous data sequence with all elements of the same sense during its passage through a transmission channel to generate regular clocking transitions comprising

first means for storing successive data bits arranged in order of occurrence,

means for half-adding pairs of selected bits from said first storing means to form individual bits of a key signal,

means responsive to a succession of data bits all of one particular sense stored in said first means for generating a "one" digit in said key signal,

further means for half-adding bits of said key signal to said data sequence to form a quasi-random line signal for application to said transmission channel and to said first storing means,

second means for storing successive bits of the line signal from said transmission channel arranged in order of occurrence,

means for half-adding pairs of selected bits from said second storing means to reconstitute the individual bits of said key signal,

further means responsive to a succession of data bits all of said one particular sense stored in said second means for generating a "one" digit in said key signal, and

final means for half-adding bits of said key signal to said line signal to restore said continuous data sequence.

3. Means for randomizing a binary data signal pattern comprising

a multi-stage shift register,

a first EXCLUSIVE-OR circuit combining the contents of a pair of stages of said shift register to form a key signal bit,

a second EXCLUSIVE-OR circuit combining each said key signal bit with a data signal bit to form a randomized line signal, and

means for applying said line signal to the first stage of said shift register.

4. Means for recovering a binary data signal pattern from a randomized line signal containing a key signal comprising

a multi-stage shift register,

means for applying said line signal to the first stage of said shift register,

a first EXCLUSIVE-OR circuit combining the contents of a pair of stages of said shift register to reconstruct said key signal bit by bit, and

a second EXCLUSIVE-OR circuit combining said line signal and said key signal to form said data signal pattern.

5. In combination with a binary data signaling system including a data source, a transmission channel and a data sink:

means at the near end of said transmission channel for breaking up a nonrandom all-space or alternating mark and space signal pattern into a random bit sequence comprising

a transmitting shift register having a fixed number of stages,

a first half-adder combining the contents of two of the stages of said transmitting shift register modulo-two fashion thereby generating a random key signal,

a second half-adder combining the key signal from said first half-adder modulo-two fashion with the nonrandom data signal from said source to form a randomized line signal,

a first coincidence circuit monitoring all stages of said transmitting shift register and producing an output if and only if all stages are storing spacing bits,

means for applying the output of said first coincidence circuit to said second half-adder as an additional key signal bit,

a clock circuit for synchronizing said data source with advance signals for said transmitting shift register,

means introducing said randomized line signal into said transmission channel; and

means at the far end of said transmission channel for reconstructing the original nonrandom signal pattern from said randomized line signal comprising

a receiving shift register having the same fixed number of stages as said transmitting shift register,

a third half-adder combining the contents of two of the stages of said receiving shift register modulo-two fashion thereby regenerating said random key signal,

a fourth half-adder combining said line signal with the key signal from said third half-adder modulo-two fashion thereby reconstructing the nonrandom signal pattern for delivery to said data sink,

a second coincidence circuit monitoring all stages of said receiving shift register and producing an output if and only if all stages are storing spacing bits,

means for applying the output of said second coincidence circuit to said fourth half-adder as an additional key signal bit, and

a clock recovery circuit for synchronizing said data sink with advance signals for said receiving shift register.

6. In combination with a binary data signaling system including a data source, a transmission channel and a data sink:

means at the near end of said transmission channel for breaking up an alternating mark and space signal pattern into a random bit sequence comprising

a transmitting shift register having a fixed number of stages,

a first half-adder combining the contents of at least two stages of said transmitting shift register modulo-two fashion thereby generating a random key signal,

a second half-adder combining the key signal from said first half-adder modulo-two fashion with the data signal from said source to form a randomized line signal,

a clock circuit for synchronizing said data source with advance signals for said transmitting shift register, and

means introducing said randomized line signal into said transmission channel; and

means at the far end of said transmission channel for reconstructing the original signal pattern from said randomized line signal comprising

a receiving shift register having the same fixed number of stages as said transmitting shift register,

a third half-adder combining the contents of at least two stages of said receiving shift register modulo-two fashion thereby regenerating said random key signal,

a fourth half-adder combining said line signal with the key signal from said third half-adder modulo-two fashion thereby reconstructing the nonrandom signal pattern for delivery to said data sink, and

a clock recovery circuit for synchronizing said data sink with advance signals for said receiving shift register.

7. The combination of claim 6 in which first coincidence circuits monitor the outputs of the odd-numbered stages of said transmitting and receiving shift register to indicate that all such stages store signals of the same sense,

second coincidence circuits monitor the outputs of even-numbered stages of said transmitting and receiving shift registers and indicate the simultaneous storage of signals of the sense opposite to that in said odd-numbered stages, and

third coincidence circuits combining the outputs of said first and second coincidence circuits to inhibit the outputs of said second and fourth half-adders and thereby insure a random line signal when the shift registers store an alternating signal sequence.

8. Self-synchronous apparatus adapted to transform an input binary signal into an output binary signal, one of said binary signals being randomized data, comprising:

means for inputting the randomized data to a key register having a plurality of locations for storing binary digits;

means for constructing a binary key signal by modulo-two combination of digits appearing at the outputs of two selected locations of said key register; and

means for combining the key signal with the input binary signal to form the output binary signal.

9. Apparatus as set forth in claim 8 in which the key register is a shift register having at least three stages and the selected locations are the last two stages.

10. Apparatus as set forth in claim 8 in which the means for constructing a key signal comprises an EXCLUSIVE-OR circuit.

11. Apparatus as set forth in claim 8 in which said combining means comprises an EXCLUSIVE-OR circuit.

12. Self-synchronous apparatus as set forth in claim 8 and means responsive to all digits stored in the key register locations being of the same sense for generating a "one" digit in the key signal to randomize a steady signal pattern with all elements of the same sense.