Decoder circuitry for selectively activating loads

• US 4,305,060 A
• Filed: 02/26/1979
• Issued: 12/08/1981
• Est. Priority Date: 02/26/1979
• Status: Expired due to Term

• Current Assignee: Whistler Corporation of Massachusetts
• Original Assignee: Multi-Elmac Company
• Inventors: Jacob, Keith D., Apple, William C.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US06/015,495
• Time in Patent Office: 1,016 Days
• Field of Search: 340/164 R, 340/168 B, 340/167 R, 340/168 R, 340/347 C, 343/225, 178/22
• US Class Current: 340/12.18
• CPC Class Codes: E05F 15/77 using wireless control
• CPC Class Codes: E05Y 2900/106 for garages
• CPC Class Codes: G08C 19/28 using pulse code

Abstract

A decoder circuit for selectively activating external loads which finds particular utility in automatic garage door operators. The coincidence of a repeatedly received digital word code with an internally generated local code results in a matched signal, each of the matched signals being stored in an accumulator device. A free running oscillator is used to reset the accumulator if a predetermined number of successive clock pulses are generated without an intervening matched signal. If a given plurality of matched signals are received and stored in the accumulator before it is reset, the accumulator will provide an output signal to a latch which activates the load. Once set, the output latch will not be reset unless a subsequent given number of successive clock pulses are generated without an intervening matched signal. In such manner, the decoder circuitry accommodates a limited number of mismatches possibly due to interference while still maintaining significant security aspects of the decoder circuitry. The resetting of the output latch will not occur immediately upon the occurence of a subsequent mismatch but is delayed to prevent the double trip condition often encountered in the automatic garage door operator field.

Claims

1. In an automatic garage door operator system using a decoder circuit having comparison means for comparing a repeatedly received digital word code signal with an internally generated local digital word code signal on a sequential pulse-by-pulse basis, with said circuit providing a matched or mismatched output signal depending upon the coincidence between the pulses of the received and local code signals, the improvement comprising:

oscillator means for providing a series of independently generated clock pulses;

accumulator means coupled to the output of said comparison means for storing a plurality of said matched signals;

an output latch means coupled to the output of said accumulator means, operative to activate the door in response to an output signal from the accumulator;

reset means coupled to said accumulator means for clearing the contents of said accumulator upon the generation of a given number of successive clock pulses from said oscillator without an intervening matched signal being generated by said comparison means; and

said accumulator means being operative to provide said output signal to activate the garage door upon receipt of a predetermined number of matched signals regardless of their sequence before said accumulator is cleared by said reset means thereby accomodating a limited number of mismatched signals possibly due to interference.

2. The improvement of claim 1 wherein said reset means further includes means for clearing said latch means upon detection of a given number of subsequently generated clock pulses without an intervening match signal.

3. The improvement of claim 2 wherein said reset means comprises:

a plurality of flip flop stages which are sequentially activated by said clock pulses, means for resetting said flip flop stages to begin the sequential activation process over again upon receipt of a matched signal, the output of the last stage being coupled to said latch means and to said accumulator means to set both of them if the last stage is activated, and the output of a preceding stage being coupled to the accumulator to reset said accumulator alone when said preceding stage is activated whereby said latch means is cleared only when the reset means subsequently detects a greater number of clock pulses than utilized to reset the accumulator alone before it originally provided the output signal to the latch means for activating it in the first instance.

4. The improvement of claim 3 which further comprises:

generator means for generating said local code, said generator means including a counter for sequentially providing a plurality of count signals;

said counter upon reaching a predetermined count providing a match signal which is stored in said accumulator and utilized to clear the reset means whereby said reset means is re-initialized to begin counting said clock signals in order to activate the last and preceding flip-flop stages.

5. In an automatic garage door operator using a decoder system having comparison means for comparing a received signal with a local code signal, with said comparison means providing a matched signal upon coincidence between the received and local code signals, the improvement comprising:

oscillator means for generating a series of clock pulses independently of said signals;

output latch means for activating a load;

means for initially setting said output latch to activate the load in response to at least one matched signal; and

reset means for clearing said latch means only after a predetermined time delay defined by the generation of a given number of successive clock pulses from said oscillator without an intervening matched signal from said comparison means.

6. The improvement of claim 5 wherein said means for setting the latch means comprises storage means for storing a given number of matched signals from the comparison means, operative to set said latch means upon receipt of said given number of matched signals, and wherein said reset means is operative to reset said storage means after the generation of M clock pulses without an intervening matched signal, said reset means being further operative to clear said latch means after the generation of N clock pulses without an intervening matched signal, where N is greater than M.

7. In a decoder circuit for selectively activating an external load depending on the contents of a repeatedly received digital word code defined by a series of pulses having different characteristics, said decoder including comparison means for comparing on a pulse-by-pulse basis the received code with an internally generated local code, the improvement comprising:

local code generator means including a counter for sequentially providing a plurality of count signals;

oscillator means for providing a plurality of clock signals;

accumulator means coupled to said counter means, operative to store a plurality of matched signals therein, each of said matched signals being a predetermined count signal from the counter means which is generated upon coincidence of all of the pulses in the local and received codes;

output latch means coupled to said accumulator means, operative to activate a load in response to an output signal from said accumulator means;

reset means having a clock input and a reset input, said clock input being coupled to said oscillator means and said reset input being coupled for receipt of said predetermined count signal from said counter means, said reset means having an output coupled to a reset input of the accumulator means wherein said reset means clears said accumulator means after receiving a predetermined number of clock pulses unless reset beforehand by said predetermined count from said counter indicating a match between the local and received codes; and

said accumulator means being operative to provide said output signal to the latch to activate the load upon receipt of given plurality of matched signals before being reset.

8. The improvement of claim 7 wherein said reset means comprises a plurality of flip flop stages which are sequentially activated by said clock signals, the output of one flip flop stage being coupled to said latch means for resetting it if the one flip flop stage is activated, and the output of a preceding flip flop stage being coupled to the accumulator means to reset said accumulator when said preceding stage is activated.

9. The improvement of claim 8 wherein said output latch is not originally set unless a given plurality of matched signals are received by the accumulator before said preceding flip flop stage of the reset generator means clears said accumulator means, and wherein said output latch is cleared only upon activation of the one flip flop stage of the reset means which occurs after activation of said preceding flip flop stage.

10. The improvement of claim 7 wherein each of said matched signals is defined by a given count signal from said counter which is generated upon coincidence of all of the pulses in the local and received codes as well as a synchronization signal between successive codes.

11. In a decoder circuit having comparison means for comparing a received digital code signal with an internally generated local digital code signal on a pulse-by-pulse basis, with said circuit providing an output signal for activating a load if said received and local codes coincide, wherein the improvement comprises:

transistor means having an input coupled to the output of said comparison means;

a resistor-capacitor network coupled to the output of said transistor means;

reference voltage means for providing a reference voltage and

a second comparator having one input coupled to the output of the network and its other input coupled to said reference voltage means wherein said comparison means provides an error signal of a time duration equal to the difference between the pulse widths of the received and local codes, said error signal causing said transistor means to charge the capacitor and provide a voltage level to said second comparator, with said second comparator providing an output signal signifying an untolerated mismatch if said voltage level exceeds the reference voltage level.

12. The improvement of claim 11 which further comprises means coupled to said resistor-capacitor network for altering the RC time constant thereof to regulate the amount of error signal necessary to charge the capacitor above the reference voltage level.