Logic simulation machine

• US 4,306,286 A
• Filed: 06/29/1979
• Issued: 12/15/1981
• Est. Priority Date: 06/29/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Malm, Richard L., Shedletsky, John J., Cocke, John
• Primary Examiner(s): Springborn, Harvey E.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/053,444
• Time in Patent Office: 900 Days
• Field of Search: 364/200 MS File, 364/400, 364/488, 364/489, 364/490, 364/491, 364/578, 364/900 MS File, 307/207, 328/92, 328/93, 328/94
• US Class Current: 703/15
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A hardware logic simulation machine comprised of an array of specially designed parallel processors, with there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory. Logic values simulated by one processor are communicated to other processors by a switching mechanism controlled by a controller. If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.

Claims

1. A highly parallel special purpose computing system for the simulation of computer logic operations comprising:

a plurality of basic processor means for executing logic simulation functions, each of said basic processor means including a first pair of memory units for storing a description of a plurality of logic functions to be simulated by said basic processor means, one of said first pair of memory units functioning as an instruction memory for storing and providing to a logic unit selected instruction functions for carrying out logic simulation functions, and the other of said first pair of memory units serves as a function memory for storing a plurality of separate selected logic functions to be executed in said logic simulation process in accordance with said instruction functions,

second and third pairs of memory units for storing logic data value signals to be processed in accordance with said logic functions, said logic value signals including signals obtained from any of said other of said plurality of basic processor means,

said second and third pairs of memory units functioning alternatively as a current signal value memory unit and current signal input memory unit pair for storing data values undergoing simulation and as a next signal value memory unit and next signal input memory unit pair for storing data values to be next simulated,

a logic unit connected to said first, second and third pairs of memory units for obtaining logic functions from said first pair of memory units and for updating the data contents of at least one of said second and third pairs of memory units,

inter-processor switching means connected to each of said plurality of basic processor means for transferring said logic value signals from any of said basic processor means to any other of said basic processor means,

and a control processor means connected to said inter-processor switching means for providing control signals to each of said plurality of basic processor means, said control processor functioning to start and stop said basic processor means, to introduce instruction signals and data value signals into said basic processor means, and to transfer data value signals between said plurality of basic processor means.

2. A computing system according to claim 1 wherein each of said basic processor units further includes a switch select memory means for storing address information of each of said plurality of basic processor means and for entering updated logic value signals in said next signal value memory unit of said third pair of memory units of said basic processor.

3. A computing system according to claim 2 wherein said control processor includes at least six separate memory units connected to said inter-processor switch, said at least six memory units being respectively a switch select memory unit, an output signal memory unit, an input signal memory unit, an output permutation unit, an input permutation unit and an event mask memory unit,

said switch select memory unit of said control processor functioning in accordance with said switch select memories of said basic control processor means,

said output and input signal memories functioning to respectively receive and provide logic data value signals from and to said plurality of basic processor means via said inter-processor switch,

said output and input permutation memories functioning to permute the order of said transfer of data value signals to and from said output and input signal memories,

and said event mask memory unit stores event information which functions to halt the simulation processor of said computing system upon the occurrence of a simulation process event which is the same as said stored event information.

4. A computing system according to claim 3 wherein said simulation process of said system functions according to a major cycle sequence and a minor cycles sequence,

said major cycle sequence including the steps wherein said basic processor logic unit sequences in order through said instruction memory of said first pair of memory units and executes each of said instructions on a logic simulation function from said function memory of said first pair of memory units on specificated data values from said current signal value memory of said second pair of memory units, said logic unit storing the results of said executions in said next signal value memory, each separate instruction execution performed by said logic unit being referred to as a minor cycle.

5. A computing system according to claim 4 wherein said logic functions specified in said function memory of said first pair of memory units include but are not limited to AND, OR, NAND, NOR and EXOR logic functions and wherein said logic unit in each said basic processors includes means for combining said logic functions to provide additional extended logic functions.

6. A computing system according to claim 5 wherein said computing system is adapted to be connected in combination with two general purpose computing systems, a host computer and a local computer,

said host computer functioning to provide conventional support functions including but not limited to interface control, command parsing, display, code compiling and test sequences,

said local computer functioning to provide machine execution control for said computing system including but not limited to single cycle execution communication with said host computer, simulation of large storage arrays, application of test sequences, and insertion and removal of logic faults for fault simulation operation.