Method and apparatus for synthesizing a modulated carrier to reduced interchannel interference in a digital communication system

• US 4,307,464 A
• Filed: 12/26/1979
• Issued: 12/22/1981
• Est. Priority Date: 12/26/1979
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hughes, William C.
• Primary Examiner(s): NG, JIN FAY
• Application Number:
  US06/106,452
• Time in Patent Office: 727 Days
• Field of Search: 375/42, 375/56, 375/60, 375/67, 332/16 R, 370/70, 340/170, 340/310 R
• US Class Current: 332/103
• CPC Class Codes: H04L 27/2092 with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)

Abstract

The modulated carrier in a frequency-multiplexed digital communications system is synthesized with each band of the modulated carrier derived from data stored in a read-only-memory. The carrier envelope shape is selected to reduce the sidebands of the digitally modulated carrier and thus reduce interchannel interference. The read-only-memory digital output is applied to a digital-to-analog converter for synthesis of an analog voltage, representing the modulated sinusoidal carrier, having reduced higher frequency content, without the necessity for use of a costly, narrow-bandpass filter.

Claims

1. Apparatus for use in a digital communication system for synthesizing a digital-data-modulated carrier waveform for transmission via a selected medium, said digital data being a sequence of binary data bits each having one of first and second binary data values, and said carrier waveform is phase-shift-keyed by said binary data, comprising:

read-only memory means for storing at each of a multiplicity of individually addressable memory locations a data word defining each of a sequential plurality of carrier amplitudes;

counter means having an input enabled at a clock frequency for providing an output signal sequentially and cyclically counting the input clock frequency, said count output signal coupled to said memory means to sequentially and cyclically read the carrier-amplitude-defining data words stored therein from the memory locations of said memory means;

means receiving the sequential data words cyclically read out of said read-only memory means for converting each data word to an associated amplitude of an analog voltage, said analog voltage being a step-wise representation of said carrier waveform having a desired carrier frequency and a desired envelope shape;

means for low-pass filtering said analog voltage to provide a substantially sinusoidal representation of said carrier waveform;

means for modulating the substantially sinusoidal carrier waveform in accordance with each bit of digital data to be transmitted, and including means receiving the carrier waveform from said low-pass-filtering means for inverting the phase thereof;

means receiving said binary data for selecting the output of said low-pass-filtering means for transmission of said modulated carrier waveform having said first binary data value and for selecting the output of said phase inverting means for transmission of said modulated carrier waveform having said second binary data; and

means for coupling the data modulated carrier waveform to said selected medium.

2. The apparatus of claim 1, wherein said selecting means is a switch having a common terminal and first and second selectable terminals respectively receiving the signals from said low-pass filtering means and said phase inverting means, the connection between said common terminal and one of said first and second selectable terminals respectively being completed responsive to transmission of a data bit having said first and second binary data values respectively.

3. The apparatus of claim 1, wherein said clock frequency is an integer multiple of said carrier waveform frequency.

4. The apparatus of claim 1, wherein said counter means is a counter sequentially and cyclically counting in a single direction and having as many counting states as the number of said multiplicity of memory locations, each counting state addressing and reading stored data from an associated one of the memory locations in said read-only memory means.

5. Apparatus for use in a digital communication system for synthesizing a digital-data-modulated character waveform for transmission via a selected medium, comprising:

read-only memory means for storing at each of a multiplicity of individually addressable memory locations a data word defining each of a sequential plurality of carry amplitudes, the data words stored in said multiplicity of memory locations in said read-only memory means defining each of a sequential plurality of band-pass-filtered carrier amplitudes for the carrier waveform in a first half of a time interval during which a single bit of data is to be transmitted;

bi-directional up/down counter means having an input enabled at a clock frequency, an output at which is provided an output signal sequentially and cyclically counting the input clock frequency, and a control input enabling the count at said output to respectively increase and decrease responsive to first and second control signals present thereat;

means receiving the sequential data words cyclically read out of said read-only memory means for converting each data word to an associated amplitude of an analog voltage, said analog voltage being a step-wise representation of said carrier waveform having a desired carrier frequency and a desired envelope shape;

control means receiving said clock frequency for providing said first control signal to said counter control input to enable said output count ot sequentially address the plurality of memory locations defining said carrier amplitudes during said first half of said bit time interval and providing said second control signal to said counter control input for reversing the count of said counter to cause said memory means addresses to sequentially return through all memory location addresses during the second half of said bit time interval, to provide therein carrier amplitudes which are the mirror image of the carrier amplitudes provided during said first half of said bit time interval;

means for low-pass filtering said analog voltage to provide a substantially sinusoidal representation of said carrier waveform; and

means for modulating the substantially sinusoidial carrier waveform in accordance for coupling data modulated carrier waveform to said selected medium.

6. The apparatus of claim 5, wherein said digital data is a sequence of binary data bits each having one of first and second binary data values, and said carrier waveform is differential-phase-shift modulated by said binary data bit sequence;

said modulating means including means for reversing the phase of said carrier waveform only when a bit having said first binary data value is to be transmitted and for maintaining the phase of said carrier waveform when a bit having said second binary data value is to be transmitted.

7. The apparatus of claim 6, wherein said phase reversing means is a linear phase inverter having a first input receiving the carrier waveform from said low-pass-filtering means, a second input receiving the binary data value of each bit of data to be transmitted, and an output at which a carrier waveform appears with a phase inversion occurring for each transition in the data bit sequence at said second input, the phase of said carrier waveform at said linear inverter output remaining substantially constant when a transition does not occur for a data bit then being transmitted.

8. The apparatus of claim 5, wherein said digital data is a sequence of binary data bits, each having one of first and second binary data values, and such carrier waveform as phase-shift-keyed by said binary data;

said modulating means including means receiving the carrier waveform from said low-pass-filtering means for inverting the phase thereof; and

means receiving said binary data for selecting output of said low-pass-filtering means for transmission of said modulated carrier waveform having said first binary data value and for selecting the output of said phase inverting means for transmission of said modulated carrier waveform having said second binary data value.

9. The apparatus of claim 8, wherein said selecting means is a switch having a common terminal at first and second selectable terminals respectively receiving the signals form said low-pass-filtering means and said phase inverting means, the connection between said common terminal and one of said first and second selectable terminals respectively being completed response to transmission of a data bit having said first and second binary data values respectively.

10. The apparatus of claim 5, wherein said clock frequency is an integer multiple carrier waveform frequency.

11. A method of synthesizing a digital data modulated carrier waveform for transmission in a digital communication system, wherein said digital data is a sequence of binary data bits each having one of first and second binary data values, comprising the steps of:

(a) storing a multiplicity of data words each defining a sequential one of a multiplicity of amplitudes of a carrier waveform having a selected envelope shape;

(b) sequentially and cyclically reading each of the data words;

(c) converting each of the sequentially cyclically read data words directly to an associated amplitude of an analog voltage to provide a step-wise representation of said carrier waveform at a desired carrier frequency and having a desired envelope shape;

(d) filtering the step-wise carrier waveform representation analog voltage to reduce the harmonic content thereof at frequencies above the desired carrier frequency; and

(e) simultaneously providing said carrier waveform analog voltage at a reference phase and at another phase substantially shifted 180°

therefrom; and

(f) selecting one of the reference phase and substantially 180°

shifted phase for transmission responsive to a data bit respectively having one of the respective first and second binary data values.

12. The method of claim 11, further comprising the step of (f) linearly amplifying the modulated carrier waveform analog voltage prior to transmission.

13. The method of claim 12, wherein the linearly amplifying step is carried out only when digital is to be transmitted.

14. The method of claim 11, wherein step (b) includes the step of sequentially and cyclically reading the stored data words in a single direction.

15. A method for synthesizing a modulated data carrier waveform for transmission in a digital communication system, comprising the steps of:

(a) storing a multiplicity of data words each defining a sequential one of a multiplicity of carrier amplitudes of a carrier waveform having a selected envelope shape for only a first half of a time interval in which a data bit is to be transmitted;

(b) sequentially reading all the stored data words in a first direction during the first half of the data bit time interval;

(c) then reading the stored data words in reverse order during a remaining half of the data bit time interval to provide a mirror image of carrier waveform amplitudes generated during the first half of the data bit time interval;

(d) converting each of the sequentially cyclically read data words to an associated amplitude of an analog voltage to provide a step-wise representation of said carrier waveform at a desired carrier frequency and having a desired envelope shape;

(e) filtering the step-wise carrier waveform representation analog voltage to reduce the harmonic content thereof at frequencies above the desired carrier frequency; and

(f) varying the phase of the filtered carrier waveform analog voltage in accordance with the data value of each bit of the digital data to be transmitted.

16. The method of claim 15, wherein step (e) includes the step of differentially phase-shift modulating the carrier waveform analog voltage in accordance with the data value of each bit of the digital data to be transmitted.

17. The method of claim 16, wherein said digital data is a sequence of binary data bits each having one of first and second binary data values, and said differentially phase-shift modulating step includes the steps of:

reversing the phase of said carrier waveform analog voltage only when said first binary data value is to be transmitted for a bit of digital data; and

maintaining the phase of said carrier waveform analog voltage when a bit of digital data having the second binary data value is to be transmitted.

18. The method of claim 17, wherein the step of reversing the phase of said carrier waveform occurs for each transition from one of said first and second binary data values to the remaining one of said first and second binary data values of any bit of the digital data to be transmitted.

19. The method of claim 15, wherein step (e) includes the step of phase-shift keying the carrier waveform analog voltage in accordance with the data value of each bit of the digital data to be transmitted.

20. The method of claim 19, wherein said digital data is a sequence of binary data bits each having one of first and second binary data values, and said phase-shift keying step includes the steps of simultaneously providing said carrier waveform analog voltage at a reference phase and another phase substantially shifted when 180°

therefrom and; and

selecting one of the reference phase and substantially 180°

shifted phase for transmission responsive to a data bit respectively having one of the respective first and second binary data values.