Array driver

• US 4,308,595 A
• Filed: 12/19/1979
• Issued: 12/29/1981
• Est. Priority Date: 12/19/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Houghton, Russell J.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/105,070
• Time in Patent Office: 741 Days
• Field of Search: 307/238, 307/279, 365/189, 365/203, 365/206, 365/208
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/411 using bipolar transistors only

Abstract

This describes a bipolar dynamic RAM cell array in which there is provided a plurality of capacitive storage data cells each being coupled to a respective capacitively loaded bit line and to one another through a common word line. A supply means is coupled to the word line for biasing each cell of the array with respect to its respective bit line to cause the bit line capacitance to set the conductive state of each cell so as to set the respective capacitive storage means of each cell to a selected charge state. The rate at which the storage means of any one cell reaches a selected state is a function of the charge state of any cell, and its respective bit line capacitance, positioned between the selected cell and the supply means.

Claims

1. In a memory array

a plurality of data cells,

a word line,

a plurality of bit lines

each bit line having a distributed capacitance,

each of said cells comprising a bipolar transistor, having a base, an emitter, and a collector, connected to a respective bit line and to said word line, and a capacitive charge storage means,

said respective bit line being connected to the base of the transistor, said word line being connected to the emitter of said transistor and said charge storage means being connected to the collector of said transistor,

means coupled to each of said cells for charging the charge storage means and the distributed capacitance on the bit lines coupled to selected cells,

current supply means coupled to the word line, and

means for selectively turning on said current supply means to supply current to the word line and set a selected voltage on the word line and cause the bit line distributed capacitance charged to a voltage, with respect to said word line, sufficient to turn the transistor to which it is coupled and closest to the current supply means, to turn on the cell transistor to which it is coupled to discharge the cell storage means through the collector emitter path of the turned on cell transistor and to discharge the charge state of the said distributed capacitance through the base emitter path of said turned on cell transistor, the rate at which any one cell storage means is discharged being a function of the charge state of the charge storage means and the bit line distributed capacitance coupled to each cell between said one cell and said supply means.

2. The array of claim 1 wherein said transistor comprises a npn transistor and each cell further includes a pnp transistor having an emitter, a base and a collector, said array further includes a second word line connected to the emitter of said pnp transistor and said supply means comprises a bipolar transistor coupled to a fixed potential.

3. In a memory array,

a pair of word lines,

a plurality of bit lines,

each bit line having a distributed capacitance,

a plurality of data cells,

each of said cells comprising a pnp transistor and an npn transistor each having an emitter, a base and a collector,

each of said cells further being connected to a respective bit line and between said pair of word lines and to a capacitive storage means

one of said word lines being connected to the emitter of the npn transistor,

the other of said word lines being connected to the emitter of said pnp transistor,

first current supply means coupled to a first one of said word lines to charge the storage means coupled to selected cells through a first one of said transistors, in said selected cells

second current supply means coupled to the other of said word lines to discharge the charged storage means and the distributed capacitance coupled to selected cells through the other one of said transistors in said selected cells the rate at which any one cell charge storage means discharges being a function of the charge state of the charge storage means and the bit line distributed capacitance coupled to each cell between said one cell and said supply means.

4. The array of claim 3 wherein each of said bit lines is further coupled to a respective sense transistor.

5. The array of claim 3 wherein said first current supply means comprises a npn transistor having its collector coupled to a voltage and its emitter coupled to one of said word lines and said second current supply means comprises an npn transistor having its collector coupled to the other of said word lines and its emitter coupled to ground,

the base of the npn transistor and the collector of the pnp transistor in each cell being connected to a respective bit line, and

the base of the pnp transistor and the collector of the npn transistor in each cell being coupled to the capacitive charge storage means of said cell.