Apparatus and methods for synchronizing a digital receiver

• US 4,308,619 A
• Filed: 12/26/1979
• Issued: 12/29/1981
• Est. Priority Date: 12/26/1979
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hughes, William C.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/106,453
• Time in Patent Office: 734 Days
• Field of Search: 375/8, 375/9, 375/106, 375/110, 375/118, 375/119, 375/120, 455/257, 455/258, 455/260, 455/265, 340/171 R, 340/310 A, 340/310 R, 328/58, 328/133, 328/155, 331/1 A, 331/14, 331/19, 329/122, 329/124
• US Class Current: 375/373
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Apparatus for synchronizing the bit clock in a digital receiver to be in phase with bits of a received data stream, utilizes a frequency source locked to a system-wide frequency and frequency-arithmetic means for providing first and second local frequencies respectively slightly greater and slightly less than a multiple of the system-wide frequency. Countdown circuitry provides a multiplicity of local clock phases at the local clock frequency for phase comparison with the clock frequency derived from the received data stream and for subsequent digital phase adjustment to cause the local baud clock to track the received data stream bit transition frequency.

Claims

1. A method for synchronizing the transition frequency of a local baud clock digital signal of a receiver in a digital communication system, to the exact baud frequency and phase of a received data bit transition stream, comprising the steps of:

(a) generating a first digital signal having a local clock frequency f_y which is a first integer multiple of the nominal baud transition frequency of said received data bit transition stream;

(b) generating a second digital signal having an offset frequency f_z which is less than the first digital signal frequency f_y ;

(c) adding said second frequency digital signal to said first frequency digital signal to provide a digital signal having a higher local transition frequency (f_y +f_z);

(d) subtracting said second frequency digital signal from said first frequency digital signal to provide a digital signal having a lower local transition frequency (f_y -f_z);

(e) selecting one of the higher and lower local transition frequency signals;

(f) dividing the selected local transition frequency signal by said first integer to obtain said local baud clock digital signal;

(g) comparing the transition frequency of said local baud clock digital signal to the exact baud clock transition frequency of the received data bit transition stream to obtain an error signal; and

(h) monitoring the error signal to select the remaining one of the higher and lower local transition frequency signals for division by the first integer to obtain the local baud clock digital signal if the error signal exceeds a predetermined limit.

2. The method of claim 1, wherein step (b) includes the step of selecting the offset frequency f_z to be a second integer multiple of the nominal baud transition frequency of said received data bit transition stream.

3. The method of claim 1, further including the step (i) of selecting the first digital signal for division by said first integer to obtain a local baud clock transition signal having said nominal baud transition frequency when a data bit stream is not received.

4. The method of claim 1, wherein step (f) includes the steps of providing a plurality of local baud clock digital signals each having a transition phase different from the transition phases of the remaining baud clock digital signals;

and selecting a local baud clock digital signal of desired transitional phase for comparison to the baud frequency of the received data bit transition stream.

5. The method of claim 4, further including the step of selecting the transition phases of each of the plurality of local baud clock digital signals to have essentially equal transition phase differences therebetween.

6. The method of claim 4, further including the step of selecting the local baud clock digital signal to be one of the local baud clock digital signal transition phases other than the local baud clock digital signal transition phase compared to the received data bit transition stream baud frequency.

7. The method of claim 1, wherein steps (a) and (b) include the steps of setting the first and second integer multiples to be respectively 2^Lo and 2^L 1 times the baud frequency of the received data bit transition stream, where L_o is an integer greater than another integer L₁ ;

and step (f) includes the step of dividing the selected signal by 2^Lo.

8. The method of claim 1, wherein the exact baud frequency is a sub-harmonic of a system-wide frequency.

9. The method of claim 8, wherein the system is a powerline communication system and the system-wide frequency is the powerline frequency.

10. The method of claim 9, wherein the exact baud frequency is the first sub-harmonic of the instantaneous powerline frequency.

11. Apparatus for synchronizing the transition frequency of a local baud clock digital signal of a receiver in a digital communication system, to the exact baud transition frequency and phase of a received data bit transition stream, comprising:

(a) first means for generating first and second digital signals having first and second local transition frequencies offset to be respectively greater than and less than the transition frequency of a local digital signal which is a first integer multiple of the nominal baud transition frequency of said received data bit transition stream;

(b) second means for selecting one of said first and second digital signals;

(c) third means for dividing the digital signal selected by said second means by said first integer to obtain said local baud clock digital signal having a transition frequency either above or below said received data bit stream baud transition frequency;

(d) fourth means for generating an error signal of magnitude responsive to the transition frequency difference between said local clock digital signal and received data bit stream baud transition frequencies; and

(e) fifth means for detecting said error signal exceeding a predetermined value to cause said second means to select the remaining one of said first and second digital signals for coupling to said third means to reduce the error signal and synchronize said local clock signal frequency transitions to the exact baud frequency transitions of said received data bit transition stream.

12. The apparatus of claim 11, wherein said first means includes means generating a digital signal having a local transition frequency f_y which is an integer multiple of the nominal baud transition frequency of the received data bit transition stream;

means generating another digital signal having an offset transition frequency f_z less than the local transition frequency f_y ;

means for digitally adding said offset transition frequency f_z signal to said local transition frequency f_y signal to provide said first local signal at a transition frequency of (f_y +f_z); and

means for digitally subtracting said offset transition frequency f_z signal from said local transition frequency f_y signal to provide said second local signal at a transition frequency of (f_y -f_z).

13. The apparatus of claim 12, wherein said offset transition frequency is another integer multiple of said received data bit transition stream band frequency.

14. The apparatus of claim 13, wherein said local transition frequency f_y is a binary multiple 2^Z of said offset transition frequency f_z ;

said offset transition frequency generating means being a Z-stage binary frequency divider having an input receiving said local transition frequency f_y signal and an output at which said offset transition signal appears.

15. The apparatus as set forth in claim 14, wherein said local transition frequency f_y is a binary multiple 2^P of said received data bit transition stream baud frequency;

and said third means is a P-stage binary frequency divider having an input receiving said selected one of said first and second digital signals and an output at which said local baud clock digital signal appears.

16. The apparatus as set forth in claim 12, wherein said transition frequency adding means comprises an exclusive-OR gate having a first input receiving said local transition frequency f_y signal and a second input receiving said offset transition frequency f_z signal, and an output at which a waveform appears having a transition frequency equal to the sum of the local and offset transition frequencies.

17. The apparatus of claim 16, further comprising a flip-flop logic element having a data input receiving said offset transition frequency f_z signal and a clock input receiving a digital signal having a transition frequency which is an integer multiple of said local transition frequency f_y, and having an output which is the only connection to said second input of said exclusive-OR gate.

18. The apparatus of claim 12, wherein said transition subtracting means comprises a first flip-flop logic element having a data input continuously receiving an enabling logic level, a clock input receiving the offset transition frequency f_z signal, a reset input and a true Q output;

a second flip-flop logic element having a data D input connected to the true Q output of said first flip-flop logic element, a clock C input, and an inverted Q output connected to the reset R input of said first flip-flop logic element; and

a NOR gate having a first input connected to the true Q output of said second flip-flop logic element and a second input connected to said clock C input of said second flip-flop logic element and receiving said local transition frequency signal f_y signal, and an output at which a waveform appears having a transition frequency equal to the difference of the local and offset transition frequencies.

19. The apparatus of claim 11, wherein said local transition frequency f_y is selected to be said integer multiple of said received data bit transition stream baud frequency;

and further comprising sixth means for providing said third means with said local transition frequency f_y signal when said received data bit transition stream signal is not present.

20. The apparatus of claim 19, wherein said sixth means includes switch means for selectively coupling either the selected transition frequency output of said second means or said first digital signal to said third means respectively responsive to the presence and absence of said received data bit transition stream.

21. The apparatus of claim 11, wherein said third means includes means for generating a plurality of said local baud clock transition frequency signals each having a transition phase different from the transition phases of the remaining local baud clock transition frequency signals;

and means for selecting a desired one of the differently-phased local baud clock transition frequency signals as the local baud clock transition signal for use in said receiver.

22. The apparatus of claim 21, wherein said means for generating said differently-phased plurality of local baud clock transition frequency signals is a Johnson counter.

23. The apparatus of claim 22, wherein said means for selecting the desired one of said plurality of differently-phased local baud clock transition frequency signals includes at least one logic gate.

24. The apparatus of claim 11, wherein said fourth means is a phase detector receiving said local baud clock digital signal at the first input thereof and said received data bit transition stream at a second input thereof and having an output at which said error signal is generated responsive to the phase difference between the transitions of the signals at said first and second inputs.

25. The apparatus of claim 24, further including means for low-pass filtering the signal at the output of said phase detector and providing the low-pass-filtered signal as the error signal to said fifth means.

26. The apparatus of claim 24, wherein said phase detector includes a two-input exclusive-OR gate.

27. The apparatus of claim 24, wherein said phase detector comprises means for providing a uni-polar pulse for each transition of said received data bit stream signal;

and means receiving said uni-polar pulses and said local baud clock digital signal for providing said error signal as an analog voltage with a preselected magnitude if each of said uni-polar pulse occurs at a time essentially at a transition of said local baud clock digital signal and with a magnitude which is greater or less than the said preselected magnitude of said uni-polar pulse occurs other than at said local baud clock digital signal transition.

28. The apparatus of claim 27, wherein said analog voltage providing means comprises a first JK-type flip-flop logic element having J and K inputs receiving a substantially constant enabling logic level, a clock C input receiving the local baud clock digital signal and having a true Q output and an inverted Q output changing logic states responsive to transitions of the local baud clock digital signal;

first and second flip-flop logic elements each having a first (J) input respectively connected to the true Q and inverted Q outputs of said JK-type flip-flop element;

a clock C input receiving uni-polar pulses, a reset R input and a true Q output having logic signal states controlled by the state of the signals at the first J, reset R and clock C inputs;

first and second NOR gates each having a first input receiving said local baud clock digital signal, a second input each respectively connected to a respective one of said JK flip-flop element true Q and inverted Q outputs, and an output respectively connected to the reset R input of a respective one of the first and second flip-flop elements;

first and second exclusive-OR gates each having first and second inputs respectively connected to the true Q output and the first J input of a respective one of the first and second flip-flop elements, and an output; and

a lowpass filter including first and second resistance elements connected in series between the outputs of said first and second exclusive-OR gates and first and second filter capacitances connected between a junction formed between said first and second resistance elements and opposites ones of opposed polarity operating potentials of substantially identical magnitudes;

said analog voltage error signal being provided at said junction.

29. The apparatus of claim 11, wherein said fifth means includes a voltage comparator having a first input receiving said error signal, a second input receiving a substantially constant comparison voltage and an output enabling said second means to select said one and said remaining one, respectively, of said first and second digital signals if the magnitude of the voltage at the voltage comparator first input is respectively greater than and less than said comparison voltage magnitude at said second voltage comparator input.