Apparatus and methods for synchronizing a digital receiver
First Claim
1. A method for synchronizing the transition frequency of a local baud clock digital signal of a receiver in a digital communication system, to the exact baud frequency and phase of a received data bit transition stream, comprising the steps of:
- (a) generating a first digital signal having a local clock frequency fy which is a first integer multiple of the nominal baud transition frequency of said received data bit transition stream;
(b) generating a second digital signal having an offset frequency fz which is less than the first digital signal frequency fy ;
(c) adding said second frequency digital signal to said first frequency digital signal to provide a digital signal having a higher local transition frequency (fy +fz);
(d) subtracting said second frequency digital signal from said first frequency digital signal to provide a digital signal having a lower local transition frequency (fy -fz);
(e) selecting one of the higher and lower local transition frequency signals;
(f) dividing the selected local transition frequency signal by said first integer to obtain said local baud clock digital signal;
(g) comparing the transition frequency of said local baud clock digital signal to the exact baud clock transition frequency of the received data bit transition stream to obtain an error signal; and
(h) monitoring the error signal to select the remaining one of the higher and lower local transition frequency signals for division by the first integer to obtain the local baud clock digital signal if the error signal exceeds a predetermined limit.
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Abstract
Apparatus for synchronizing the bit clock in a digital receiver to be in phase with bits of a received data stream, utilizes a frequency source locked to a system-wide frequency and frequency-arithmetic means for providing first and second local frequencies respectively slightly greater and slightly less than a multiple of the system-wide frequency. Countdown circuitry provides a multiplicity of local clock phases at the local clock frequency for phase comparison with the clock frequency derived from the received data stream and for subsequent digital phase adjustment to cause the local baud clock to track the received data stream bit transition frequency.
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Citations
29 Claims
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1. A method for synchronizing the transition frequency of a local baud clock digital signal of a receiver in a digital communication system, to the exact baud frequency and phase of a received data bit transition stream, comprising the steps of:
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(a) generating a first digital signal having a local clock frequency fy which is a first integer multiple of the nominal baud transition frequency of said received data bit transition stream; (b) generating a second digital signal having an offset frequency fz which is less than the first digital signal frequency fy ; (c) adding said second frequency digital signal to said first frequency digital signal to provide a digital signal having a higher local transition frequency (fy +fz); (d) subtracting said second frequency digital signal from said first frequency digital signal to provide a digital signal having a lower local transition frequency (fy -fz); (e) selecting one of the higher and lower local transition frequency signals; (f) dividing the selected local transition frequency signal by said first integer to obtain said local baud clock digital signal; (g) comparing the transition frequency of said local baud clock digital signal to the exact baud clock transition frequency of the received data bit transition stream to obtain an error signal; and (h) monitoring the error signal to select the remaining one of the higher and lower local transition frequency signals for division by the first integer to obtain the local baud clock digital signal if the error signal exceeds a predetermined limit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. Apparatus for synchronizing the transition frequency of a local baud clock digital signal of a receiver in a digital communication system, to the exact baud transition frequency and phase of a received data bit transition stream, comprising:
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(a) first means for generating first and second digital signals having first and second local transition frequencies offset to be respectively greater than and less than the transition frequency of a local digital signal which is a first integer multiple of the nominal baud transition frequency of said received data bit transition stream; (b) second means for selecting one of said first and second digital signals; (c) third means for dividing the digital signal selected by said second means by said first integer to obtain said local baud clock digital signal having a transition frequency either above or below said received data bit stream baud transition frequency; (d) fourth means for generating an error signal of magnitude responsive to the transition frequency difference between said local clock digital signal and received data bit stream baud transition frequencies; and (e) fifth means for detecting said error signal exceeding a predetermined value to cause said second means to select the remaining one of said first and second digital signals for coupling to said third means to reduce the error signal and synchronize said local clock signal frequency transitions to the exact baud frequency transitions of said received data bit transition stream. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification