Complementary amplifier circuit
First Claim
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1. A complementary amplifier circuit comprising:
- first and second potential sources;
a first FET of a first conductivity having a gate connected to an input terminal, a source connected to said first potential source and a drain;
a second FET of a second conductivity type having a gate, a source connected to said second potential source and a drain;
first connecting means connected between the drains of said first and said second FETs;
bias resistive means connected between the gate and the drain of said first FET;
a capacitor connected between the gates of said first and second FETs;
a third FET of said second conductivity type having a gate connected to the gate of said second FET, a source connected to the source of said second FET and a drain;
second connecting means connected between the drain and the gate of said third FET; and
load means connected between said first potential source and the drain of the third FET.
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Abstract
A complementary amplifier circuit includes a p-channel MISFET and an n-channel MIS connected in series. The gate of the p-channel FET transistor is D.C. biased by a high impedance resistor connected between the gate and drain electrodes, and the gate of the n-channel FET is D.C. biased by a current mirror circuit formed by another n-channel FET. This complementary amplifier circuit has the advantages that the operational lower limit voltage thereof is equal to the threshold voltage of one of the MOSFETs and that stabilized operation of the amplifier is easily obtained.
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8 Claims
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1. A complementary amplifier circuit comprising:
- first and second potential sources;
a first FET of a first conductivity having a gate connected to an input terminal, a source connected to said first potential source and a drain;
a second FET of a second conductivity type having a gate, a source connected to said second potential source and a drain;
first connecting means connected between the drains of said first and said second FETs;
bias resistive means connected between the gate and the drain of said first FET;
a capacitor connected between the gates of said first and second FETs;
a third FET of said second conductivity type having a gate connected to the gate of said second FET, a source connected to the source of said second FET and a drain;
second connecting means connected between the drain and the gate of said third FET; and
load means connected between said first potential source and the drain of the third FET. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- first and second potential sources;
Specification