Process for producing a calibrated resistance element

• US 4,310,571 A
• Filed: 04/27/1979
• Issued: 01/12/1982
• Est. Priority Date: 04/28/1978
• Status: Expired due to Term

• Current Assignee: Sgs-Ates Componenti Elettronici SPA (STMicroelectronics NV)
• Original Assignee: Sgs-Ates Componenti Elettronici SPA (STMicroelectronics NV)
• Inventors: Daniele, Vincenzo, Corda, Giuseppe, Ravaglia, Andrea, Ferla, Giuseppe
• Primary Examiner(s): Smith, John D.
• Application Number:
  US06/034,204
• Time in Patent Office: 991 Days
• Field of Search: 427/96, 427/102, 427/103, 357/51, 156/643, 156/653, 156/652, 29/620
• US Class Current: 427/102
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: Y10T 29/49082 Resistor making
• CPC Class Codes: Y10T 29/49099 Coating resistive material on a base

Abstract

Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO₂ and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.

Claims

1. A process for producing a calibrated resistance element on a substrate, comprising the steps of:

(a) depositing a dielectric layer attackable by a chemical agent on said substrate;

(b) topping said dielectric layer with a coating of a different material resistant to attack by said agent;

(c) destroying part of said coating to leave a residue with at least one exposed lateral edge;

(d) subjecting said dielectric layer to an isotropic attack by said agent with resulting reduction in the thickness of said layer except for a pedestal supporting said residue and with erosion of the periphery of said pedestal underneath said exposed edge whereby an elongate undercut is formed in said periphery;

(e) forming a conductive deposit of predetermined resistivity on said dielectric layer at least to the level of said residue with penetration of said undercut by a filiform portion of said deposit; and

(f) removing said deposit at least along said edge while leaving intact the filiform portion thereof accumulated in said undercut.

2. A process as defined in claim 1 wherein said substrate is a semiconductor.

3. A process as defined in claim 2 wherein said semiconductor is silicon and said dielectric layer consists of silicon dioxide.

4. A process as defined in claim 3 wherein said different material is a nonconductive silicon compound.

5. A process as defined in claim 1, 2 or 3 wherein said different material is selected from the group which consists of semiconductors and metals.

6. A process as defined in claim 5, comprising the further step of cladding said residue with an insulating envelope before forming said deposit in step (e).

7. A process as defined in claim 5 wherein said different material is polycrystalline silicon.

8. A process as defined in claim 7, comprising the further step of oxidizing the surface of said residue before forming said deposit in step (e).

9. A process as defined in claim 1, 2 or 3 wherein parts of said deposit at opposite ends of said undercut are left in place in step (f) and remain electrically interconnected by said filiform portion.

10. A process as defined in claim 9 wherein said residue is a substantially rectangular patch whereby the peripheral erosion of said pedestal in step (d) forms four lateral channels in step (e), the parts of said deposit left in place in step (f) being a pair of conductor strips substantially perpendicular to two of said channels.