Phase-locked loop stabilized by a crystal oscillator

• US 4,310,805 A
• Filed: 12/13/1979
• Issued: 01/12/1982
• Est. Priority Date: 12/13/1979
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hughes, William C., Hackert, William P.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/103,032
• Time in Patent Office: 761 Days
• Field of Search: 329/50, 329/122, 331/1 A, 331/17, 331/18, 331/21, 331/25, 331/DIG. 2, 331/14, 331/23
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/185 using a mixer in the loop H03L7/187 - H03L7/195 take precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A phase-locked loop circuit, having an oscillator controlled by a voltage related to the phase difference between a reference signal and a loop signal, is stabilized by a crystal oscillator. The voltage controlled oscillator signal is frequency-subtracted from the crystal oscillator signal frequency to provide an input signal to a frequency-arithmetic synthesizer which provides a loop signal to the phase detector for comparison with the coming reference signal. Use of a frequency-adder circuit between the voltage controlled oscillator and the frequency-subtractor, and receiving an addition frequency derived from the frequency-arithmetic synthesizing circuit, is utilized to decrease the loop gain and provide enhanced characteristics.

Claims

1. Apparatus for providing at least one output frequency signal phase-locked to the frequency of an input signal, comprising:

a phase detector having first and second inputs and an output having a signal related to the difference in phase between the signals at the first and second inputs;

input signal conditioning means receiving said input signal for providing a reference frequency signal to said first phase detector input;

means connected to the phase detector output for filtering said phase detector output signal;

means receiving the filtered output signal from the filtering means for generating a periodic waveform having a first frequency controlled by the magnitude of the filtered phase detector output signal;

crystal controlled oscillator means for providing a signal at a second frequency;

frequency-subtractive means having a first input receiving a sum-frequency signal and a second input receiving the second frequency signal for providing an output signal having a third frequency equal to the difference between said sum-frequency and second signal frequency;

frequency-arithmetic means receiving the third frequency signal for synthesizing said at least one output signal and for providing a loop signal for coupling to the second input of said phase detector for causing said waveform generating means frequency to vary and lock the frequency of said at least one output frequency to said input signal frequency;

said frequency-arithmetic means also providing a signal at a fourth frequency; and

means receiving the waveform generating means output signal and said fourth frequency signal for adding the first and fourth frequency signals to provide the sum-frequency input signal to the first input of the frequency-subtractive means.

2. The apparatus of claim 1, wherein said frequency adding means comprises a two-input exclusive-OR gate having said fourth frequency signal coupled to one input thereof and having said waveform generating means output signal coupled to the other input thereof, said gate having an output at which a signal having a frequency equal to the sum of the frequencies at the inputs of the gate appears.

3. The apparatus of claim 2, further comprising a flip-flop logic element having a data input receiving the waveform generating means output signal, a clock input receiving said fourth frequency signal and an output set to the logic state at the data input only when a transition of said fourth signal appears at said clock input, said flip-flop logic element output being coupled to said first input of said exclusive OR gate.

4. The apparatus of claim 1, wherein said frequency-arithmetic means effectively divides said third frequency by a number N, and the second frequency provided by said crystal-controlled oscillator means is chosen to be greater, if effectively divided by N in said frequency arithmetic means, than the greatest expected frequency of said input signal.

5. The apparatus of claim 1, wherein the output signal frequency of said waveform generating means is about one order of magnitude less than said second frequency.

6. The apparatus of claim 1, wherein said frequency-subtractive means comprises a first flip-flop logic element having a count input receiving said first frequency signal, a clear input and an output settable to a first logic level by the appearance of a signal at said count input and to a remaining logic level by the appearance of a signal at said clear input;

a second flip-flop logic element having a count input receiving said second frequency signal, a data input connected to the output of said first flip-flop logic element, a first output settable to said first and second logic levels responsive to the appearance of said first and second logic levels at said data input, and a second output, coupled to the clear input of the first flip-flop logic element and having a signal thereat which is the inverse of the signal at the first output of said second flip-flop logic element; and

a NOR gate having a first input connected to the first output of said second flip-flop logic element and a second input receiving said second frequency signal, and an output at which said output signal having a frequency equal to the difference between said first and second signal frequencies appears.

7. The apparatus of claim 1, further comprising auxiliary frequency-arithmetic means receiving signal frequencies from said synthesizing frequency-arithmetic means for providing an additional signal at said first frequency;

and switch means activated to connect the first frequency receiving input of said frequency subtractive means to the output of said additional frequency-arithmetic means whenever said input signal is not present at said apparatus.

8. The apparatus of claim 1, wherein said frequency-arithmetic means comprises at least one counter means dividing the third signal frequency by at least one integer divisor in order to provide each of said at least one output signal and said loop signal.

9. The apparatus of claim 1, further comprising means receiving said reference frequency signal and said loop signal for indicating that a phase-quadrature condition exists therebetween.

10. The apparatus of claim 9 wherein said phase-quadrature means is connected to said filtering means for increasing the degree of filtering applied to said phase detector output signal only when said reference and loop signals are in phase quadrature.

11. The apparatus of claim 1, wherein said input signal is a powerline signal and said input signal conditioning means is a zero crossing detector.

12. The apparatus of claim 1, wherein said input signal is a continuously received phase-shift-modulated signal at a carrier frequency;

and said input signal conditioning means comprises full-wave rectifying means for providing said reference signal frequency at the second harmonic of the input carrier frequency and devoid of modulation characteristics.

13. Apparatus for providing at least one output frequency signal phase-locked to the frequency of an input signal, comprising:

a phase detector having first and second inputs and an output having a signal related to the difference in phase between the signals at the first and second inputs;

input signal conditioning means receiving said input signal for providing a reference frequency signal to said first phase detector input;

means connected to the phase detector output for filtering said phase detector output signal;

means receiving the filtered output signal from the filtering means for generating a periodic waveform having a first frequency controlled by the magnitude of the filtered phase detector output signal;

crystal controlled oscillator means for providing a signal at a second frequency;

means having a first input receiving the first frequency signal and a second input receiving the second frequency signal for providing an output signal having a third frequency equal to difference between said first and second signal frequencies and comprising;

a first flip-flop logic element having a count input receiving said first frequency signal, a clear input and an output settable to a first logic level by the appearance of a signal at said count input and to a remaining logic level by the appearance of a signal at said clear input;

a second flip-flop logic element having a count input receiving said second frequency signal, a data input connected to the output of said first flip-flop logic element, a first output settable to said first and second logic levels responsive to the appearance of said first and second logic levels at said data input, and a second output, coupled to the clear input of the first flip-flop logic element and having a signal thereat which is the inverse of the signal at the first output of said second flip-flop logic element; and

a NOR gate having a first input connected to the first output of said second flip-flop logic element and a second input receiving said second frequency signal, and an output at which said output signal having a frequency equal to the difference between said first and second signal frequencies appears; and

frequency-arithmetic means receiving the third frequency signal for synthesizing said at least one output signal and for providing a loop signal for coupling to the second input of said phase detector for causing said waveform generating means frequency to vary and lock the frequency of said at least one output frequency to said input signal frequency.

14. Apparatus for providing at least one output frequency signal phase-locked to the frequency of an input signal, comprising:

a phase detector having first and second inputs and an output having a signal related to the difference in phase between the signals at the first and second inputs;

input signal conditioning means receiving said input signal for providing a reference frequency signal to said first phase detector input;

means connected to the phase detector output for filtering said phase detector output signal;

means receiving the filtered output signal from the filtering means for generating a periodic waveform having a first frequency controlled by the magnitude of the filtered phase detector output signal;

crystal controlled oscillator means for providing a signal at a second frequency;

means having a first input receiving the first frequency signal and a second input receiving the second frequency signal for providing an output signal having a third frequency equal to one of the sum and difference between said first and second signal frequencies;

frequency-arithmetic means receiving the third frequency signal for synthesizing said at least one output signal and for providing a loop signal for coupling to the second input of said phase detector for causing said waveform generating means frequency to vary and lock the frequency of said at least one output frequency to said input signal frequency;

auxiliary frequency-arithmetic means receiving signal frequencies from said synthesizing frequency-arithmetic means for providing an additional signal at said first frequency; and

switch means activated to connect the first frequency receiving input of said third frequency providing means to the output of said additional frequent-arithmetic means whenever said input signal is not present at said apparatus.