Single line multiplexing system for sensors and actuators

• US 4,311,986 A
• Filed: 09/13/1978
• Issued: 01/19/1982
• Est. Priority Date: 09/13/1978
• Status: Expired due to Term

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Yee, Henry C.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US05/942,003
• Time in Patent Office: 1,224 Days
• Field of Search: 340/167 A, 340/147 R, 340/167 R, 340/171 R, 340/163
• US Class Current: 340/12.16
• CPC Class Codes: G01R 29/0273 the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A single line refigurable power transmission and signal multiplexing system having a central processor and a plurality of remotely located devices such as sensors, actuators and associated interfaces. Communications between the central processor and the remote devices is accomplished via a single bi-directional transmission line. A negative logic pulse width encoding technique is utilized to facilitate power and signal transmission. Selective activation is accomplished by a pulse width discriminator associated with each interface which employs a two-part recognition test to identify specific pulse width signals.

Claims

1. A system for transmitting signals between a processor and at least one remotely located device, wherein the processor generates a plurality of command signals uniquely identifying each of the remotely located device, comprising:

a bi-directional data transmission line;

interrogation signal generating means interconnecting the processor with said data transmission line for generating on said data transmission line interrogation signals having pulse widths t_i, the pulse width of each of said interrogation signal is uniquely associated with a corresponding command signal;

interface means interconnecting each remotely located device with the data transmission line for selectively enabling communication between the processor and said device in response to said interrogation signals, each interface means responsive to an interrogation signal including one of said predetermined pulse widths which is different from the predetermined pulse width to which other interface means respond;

wherein each of said interface means includes;

a pulse width discriminator for generating a trigger signal in response to an interrogation signal having a predetermined pulse width;

means responsive to said trigger signal for establishing direct communication between the device and said transmission line, and

wherein the predetermined pulse width of said interrogation signal has a time duration t₁, said pulse width discriminator comprises;

first means responsive to the beginning of each interrogation signal appearing on said transmission line, for generating a first test pulse of duration (t_i -Δ

);

second means, responsive to the termination of said first test pulse for generating a second test pulse having a duration 2Δ

where 2Δ

corresponds to a time increment smaller than t₁ ; and

third means, responsive to said interrogation signals and said second test pulse, for generating a trigger signal indicative of the condition that said interrogation signal of duration t_i has terminated during the time of said second test pulse.

2. The system as recited in claim 1 wherein said first means includes a first monostable multivibrator disposed between said transmission line and said second means, for generating said first test pulse, in response to the beginning edge of said interrogation signals, and wherein said second means includes a second monostable multivibrator, disposed between said first and said third means, responsive to the termination of said first test pulse for generating said second test pulse.

3. The system as recited in claim 2 wherein said third means includes a D-latch flip-flop having a data input terminal and a clock input, said D-latch flipflop receiving said second test pulse at said data input terminal and connected so that the state of the flipflop is clocked by the trailing edge of said interrogation signal.

4. The system as recited in claim 1 wherein at least one of said devices is a sensor which can generate a sensor signal having a value indicative of the state of a sensed parameter, and where said means responsive to said trigger signal further includes reply means activated by said trigger signal for generating a reply signal at a time after the termination of said trigger signal, the time between the termination of said trigger signal and said reply signal being related to the value of said sensed parameter.

5. The system as recited in claim 4 wherein said interrogation signal generating means further comprises:

data means responsive to said interrogation signal and said reply signal for generating a signal indicative of the value of said sensed parameter.

6. The system of claim 4 wherein said sensor generates an analog signal having a value indicative of the sensed parameter and where said reply means includes:

timer means activated by said trigger signal for generating a timer signal having a time duration indicative of the value of said analog signal;

reply signal generator means, connected to said transmission line for generating said reply signal in response to the termination of said timer signal.

7. The system of claim 6 wherein said reply signal generator means comprises:

a monostable multivibrator responsive to said timer signal for generating a reply pulse having a predetermined duration; and

a buffer amplifier connecting said monostable multivibrator to said transmission line responsive to said reply pulse for generating said reply signal and for communicating said reply signal to said bi-directional line.

8. The system of claim 7 wherein said reply signal is a pulse width signal of predetermined length and has a value equal to said second voltage potential of said interrogation signal.

9. The system as recited in claim 8 where said interface further includes:

reset means for generating a reset signal to reset said pulse width discriminator.

10. A system for transmitting signals between a processor and at least one remotely located device, wherein the processor generates a plurality of command signals uniquely identifying each of the remotely located devices, comprising:

a bi-directional data transmission line;

interrogation signal generating means interconnecting the processor with said data transmission line for generating on said transmission line pulse width modulated interrogation signals of predetermined pulse width t_i, the pulse width of each of said interrogation signals is uniquely associated with a corresponding command signal;

interface means interconnecting each remotely located device with the data transmission line for selectively enabling communication between the processor and said device in response to said interrogation signals, each interface means responsive to an interrogation signal including one of said predetermined pulse widths and the pulse width to which each interface means responds is different from the predetermine pulse widths to which other interface means respond;

wherein each of said interface means includes;

a pulse width discriminator for generating a trigger signal in response to an interrogation signal having a predetermined pulse width;

means responsive to said trigger signal for establishing direct communication between the device and said transmission line, and

where said pulse width discriminator comprises;

fourth means connected to said transmission line, including a first monostable multivibrator (266), generating an output signal and a complementary output signal responsive to the negative going edge of a pulse width signal on said transmission for generating a first test pulse of predetermined duration (t_i -Δ

); and

fifth means including a second monostable multivibrator (268) generating an output signal and a complementary output signal connected to the output of said fourth means, responsive to the negative going edge of the signal appearing at the output of said fourth means for generating a second test pulse signal of predetermined duration 2Δ

;

a logic signal inverter including a first NAND gate (258) connected to said transmission line;

D-latch flipflop (257) receiving a data input signal from the output of said logic signal inverter and receiving a clock signal from the complementary output of said fourth means;

a second NAND gate (260) receiving inputs from said transmission line and the output of said D-latch flip-flop (257) and generating an output;

a second logic signal inverter, including a third NAND gate (262) receiving the output of said second NAND gate (260);

second D-latch flip-flop (256) responsive to the output of said second logic signal inverter and further receiving a clocking signal from the complementary output of said fifth means;

fourth NAND gate means (264) responsive to the output of said second D-latch flip-flop (256) and the output of said first D-latch flip-flop (257) for generating said trigger signal indicative of the condition that said interrogation signal of duration t_i has terminated during the time of said second test pulse.

11. The system as recited in claims 3 or 10 wherein said interface means further comprises reset means for generating a reset signal to reestablish the quiescent state of the circuitry within said interface means a determinable time after selective communication with said interface means has been established.

12. The system as recited in claims 3 or 10 wherein said interrogation signal generating means comprises:

buffer means for maintaining the signal level of said bi-directional data transmission line at a first voltage potential above ground potential in the absence of signal transmissions.

13. The system as recited in claim 12 wherein said interface means further includes power storage and discharge means for storing a predetermined quantity of power, transmitted by said transmission line, of said first voltage potential for use by said pulse width discriminator and by said device means and for preventing discharge of said storage means during signal transmission on said transmission line.

14. The system as recited in claim 13 wherein said interrogation signal generating means comprises means for maintaining the voltage level of said transmission line at a second voltage potential such as at nearly ground potential, during times involving signal transmission.

15. A system for transmitting signals between a processor and at least one remotely located device, wherein at least one of said devices is an actuator and wherein the processor generates a plurality of command signals uniquely identifying each of the remotely located device, including:

a bi-directional data transmission line;

interrogation signal generating means interconnecting the processor with said data transmission line for generating on said data transmission line pulse width modulated interrogation signals of predetermined pulse widths t_i the pulse width of each of said interrogation signals is uniquely associated with a corresponding command signal and

wherein said interrogation signals further comprises a predetermined pulse width t_a, indicative of an actuator turn-on command corresponding to one of the command signals and switching between a first value to a second value wherein the time that said interrogation signal is at said second value identifies a specific actuator corresponding to the command signal and where said interrogation signal is returned to said first level for a determinable time t_d, indicative of the data command signal to be transmitted to said actuator, and where said interrogation signal is returned to said second level for a second predetermined period t_b, indicative of a turn-off command signal;

interface means interconnecting each remotely located device with the data transmission line for selectively enabling communication between the processor and said device in response to said interrogation signals, each interface means responsive to an interrogation signal including one of said predetermined pulse widths and the pulse width to which each interface means responds is different from the predetermined pulse widths to which other interface means respond, said interface means further comprising;

actuator turn-on means disposed between said transmission line and said actuator responsive to said turn on command signal, for generating a signal to turn on said actuator when said interrogation signal contains a predetermined pulse width such as t_a ; and

a pulse width discriminator for generating a trigger signal in response to an interrogation signal having a predetermined pulse width;

means responsive to said trigger signal for establishing direct communication between the device and said transmission line.

16. The system as recited in claim 15 wherein said interrogation signal generating means comprises buffer means for maintaining during times not involving signal transmission, the signal level of said bi-directional data transmission line at a first voltage potential about ground potential.

17. The system as recited in claim 16 wherein said interrogation signal generating means comprises means for maintaining the voltage level on said transmission at a second voltage potential such as at nearly ground potential during times involving signal transmission.

18. The system as recited in claim 16 wherein said interface means further includes power storage and discharge means connecting said transmission line to said device means and to said pulse width discriminator for storing a predetermined quantity of power transmitted by said transmission line of first value for use by said pulse width discriminator and by said device means and for preventing discharge of said storage means during signal transmission on said transmission line.

19. The system as recited in claim 18 wherein said interface means further comprises:

actuator turn-off means disposed between said transmission line and said actuator responsive to said turn-off command signal for generating a signal to turn off said actuator when said interrogation signal contains a second predetermined pulse width signal such as t_b.

20. The system as recited in claim 19 wherein said interface means further includes:

actuator data means for generating a data signal for use by said actuator in response to the time interval between said turn-on command signal and said turn-off command signal corresponding to the time interval t_d of said interrogation pulse.

21. The system as recited in claim 19 wherein said actuator turn-on means includes:

a pulse width discriminator responsive to the t_a portion of said interrogation signal for generating a trigger signal;

a signal storage device such as an actuator flip-flop disposed between said pulse width discriminator and said actuator, responsive to said trigger signal for generating signal to turn on said actuator when triggered by said trigger signal.

22. The system as recited in claim 19 wherein said actuator turn-off means includes:

a monostable multivibrator responsive to said turn-off portion of said interrogation signal and connected to the reset terminal of said signal storage device for generating a trigger signal, to reset said signal storage device therein causing said signal storage device to generate a deactivation signal to turn off said actuator.

23. The system as recited in claim 19 wherein said actuator turn-off means includes:

a pulse width discriminator responsive to said turn-off portion of said interrogation signal and connected to the reset terminal of said signal storage device for generating a trigger signal to reset said signal storage device therein causing said signal storage device to generate a deactivation signal to turn off said actuator.

24. The system as recited in claim 19 wherein said interface means further includes:

actuator data means interconnecting said actuator for generating a data signal to command said actuator in response to the time interval t_d between said turn-on command signal and said turn-off command signal corresponding to the time interval t_d of said interrogation pulse.

25. The system as recited in claim 22 wherein actuator data means is a pulse width-to-analog converter.

26. A system for transmitting signals between a processor and at last one remotely located device, wherein the processor generates a plurality of command signals uniquely identifying each of the remotely located device, comprising:

a bi-directional data transmission line;

interrogation signal generating means interconnecting the processor with said data transmission line for generating on said data transmission line pulse width modulated interrogation signals of predetermined pulse width t_i, the pulse width of each of said interrogation signals is uniquely associated with a corresponding command signal and wherein said interrogation signal generating means further includes;

pulse width generator means responsive to said command signals for generating signals having determinable pulse widths;

level shifting means, receiving said pulse width signals from said pulse width generator means, for translating the magnitude of said pulse width signals into amplified bilevel pulse width signals, each having a magnitude of a first level of voltage potential, and where said level shifting means is disposed between said pulse width generator means and a driver means;

driver means for impressing said translated pulse width generator means signals onto said transmission line;

composite circuitry means comprising a current limiter means interconnecting said driver means and said transmission line for limiting the output current flowing into said transmission line, and where said level shifting means said driver means and said current limiter means cooperate to establish said interrogation signals having a magnitude defined by said first level of voltage potential and a second voltage potential, such that said first level of voltage potential is impressed upon said transmission line;

interface means interconnecting each remotely located device with the data transmission line for selectively enabling communication between the processor and said device in response to said interrogation signals, each interface means responsive to an interrogation signal including one of said predetermined pulse widths and the pulse width to which each interface means responds is different from the predetermined pulse widths to which other interface means respond.

27. The signal transmission system of claim 26 where said interrogator means includes data pulse storage means for indicating the time between the transmission of said interrogation signal and receipt of said reply signal wherein said data pulse storage means is activated in response to said interrogation signal and reset upon receipt of said reply signal.

28. The system as recited in claim 26 where said composite circuitry comprises:

inhibit means for inhibiting interrogator transmitted signals from resetting said data pulse storage means; and

reply signal receipt means for resetting said data pulse storage means upon receipt of said reply signal.

29. The signal transmission system of claim 27 wherein said system further includes:

first converter means communicating with said data pulse storage means of said interrogator means for generating digital data indicative of the time that said data pulse storage means is activated.

30. The signal transmission system of claim 28 wherein said composite circuitry comprises:

a first resistor (223);

a pair of series resistors (224 and

     225) having a common terminal (231) so the one terminal of resistor (224) is connected to one terminal of resistor (225), said first resistor (223) and said pair of series resistors (224 and

     225) being connected in parallel, wherein one terminal (229) of said parallel combination is connected to the output of said driver means and the second terminal (230) of said parallel combination being connected to said transmission line;

a PNP transistor (222);

a second pair of series resistors (226 and

     228);

a second resistor (227);

an NPN transistor (234);

said one terminal (229) being connected to the emitter of said PNP transistor (222) and the base of said PNP transistor (222) is connected to said common terminal (231), the collector of said PNP transistor (222) communicating with one terminal of resistor (226), the other terminal of resistor (226) being connected in common to the base terminal of NPN transistor (234) and to one terminal of resistor (228), wherein the other terminal of resistor (228) and the emitter of said NPN transistor (234) are grounded;

said collector terminal of said NPN transistor (234) being connected to one terminal of resistor (227) and the other terminal of resistor (227) adapted to be connected to a voltage potential V₂, and where said collector of said NPN transistor (234) is adapted to communicate with the reset terminal of said data pulse storage means.

31. A ground reset system interposing signal generating stations A and B comprising:

a bi-directional transmission line for carrying signals between stations A and B; and

means connected to said bi-directional transmission line for generating a ground reset signal in response to a ground potential signal which originates at station B while ignoring ground potential signals originating at station A.

32. The ground reset system according to claim 31 wherein said means comprises:

a first voltage source;

a PNP transistor (222) having emitter, collector and base terminals, wherein said emitter terminal is connected to said first voltage source;

a first voltage divider circuit (223, 224,

     225) having a first terminal connected to said first voltage source, a second terminal connected to said bi-directional line and a third terminal connected to the base terminal of said PNP transistor;

a second voltage source;

an NPN transistor (234) having base, emitter and collector terminals, wherein said collector terminal is connected to said second voltage source, said emitter terminal is connected to ground potential and where the ground reset signal appears at said collector terminal; and

a second voltage divider circuit having a first terminal connected to the collector terminal of said PNP transistor, a second terminal connected to ground potential and a third terminal connected to the base of said NPN transistor.

33. A method of transmitting power from one location to at least one of a plurality of device means and of selectively communicating with said device means, the steps of which comprise:

energizing a transmission line at a first voltage potential;

communicating said first voltage to a storage and discharge means therein generating a stored voltage;

communicating said stored voltage to said device means;

generating processor commands identifying the specific device means;

generating a coded bi-level pulse width signal, in response to said processor commands, wherein a unique code is associated with each of said device means;

combining said coded bi-level pulse width signal with said first voltage potential to generate a negative logic coded signal in such a manner as to reduce the voltage on said transmission line to a second voltage potential for a determinable time corresponding to the pulse width t_i, assigned to a specific device means;

generating a first test pulse signal having a duration of t_i -Δ

seconds in response to the leading edge of said combined signal, wherein a different t_i is associated with each device means;

generating a second test pulse signal, in response to said first test pulse, having a duration 2Δ

seconds, where 2Δ

is a time period substantially smaller than any of said combined signals;

generating an activation signal indicative of the fact that said combined signal returned to said first voltage potential during the existence of said second test signal indicating that said combined signal was of duration t_i which is uniquely assigned to a specific device.