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Instruction buffer apparatus of a cache unit

  • US 4,312,036 A
  • Filed: 12/11/1978
  • Issued: 01/19/1982
  • Est. Priority Date: 12/11/1978
  • Status: Expired due to Term
First Claim
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1. A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:

  • instruction address register means coupled to said data processing unit, said instruction address register means including a number of bit positions for storing an address in response to a predetermined type of said commands previously received from said data processing unit, said address specifying a next instruction word to be accessed by said data processing unit;

    an addressable instruction buffer coupled to said main store and to said instruction address register means, said instruction buffer comprising a number of sections, each section comprising;

    a plurality of addressable locations for storing a sequence of instruction words received from said main store, each location including a plurality of bit positions for storing an instruction word and at least one bit position connected to switch from a first state to a second state when an instruction word is being written in said location; and

    ,control means coupled to said instruction address register means, to said processing unit to said main store and to each of said sections of said instruction buffer, said control means being operative in response to a signal corresponding to said second state received from said one bit position of one of said locations specified by said instruction address register means to generate an output signal to said processing unit, said signal indicating that said next instruction word specified by said instruction address register means has been received from said main store and is being written into one of said buffer locations of one of said sections thereby enabling said processing unit to begin immediately the processing of said next instruction specified by said instruction address register means.

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