Instruction buffer apparatus of a cache unit
First Claim
1. A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:
- instruction address register means coupled to said data processing unit, said instruction address register means including a number of bit positions for storing an address in response to a predetermined type of said commands previously received from said data processing unit, said address specifying a next instruction word to be accessed by said data processing unit;
an addressable instruction buffer coupled to said main store and to said instruction address register means, said instruction buffer comprising a number of sections, each section comprising;
a plurality of addressable locations for storing a sequence of instruction words received from said main store, each location including a plurality of bit positions for storing an instruction word and at least one bit position connected to switch from a first state to a second state when an instruction word is being written in said location; and
,control means coupled to said instruction address register means, to said processing unit to said main store and to each of said sections of said instruction buffer, said control means being operative in response to a signal corresponding to said second state received from said one bit position of one of said locations specified by said instruction address register means to generate an output signal to said processing unit, said signal indicating that said next instruction word specified by said instruction address register means has been received from said main store and is being written into one of said buffer locations of one of said sections thereby enabling said processing unit to begin immediately the processing of said next instruction specified by said instruction address register means.
0 Assignments
0 Petitions
Accused Products
Abstract
A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes an instruction buffer having first and second sections for storing instructions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each location is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location. Instruction buffer ready circuits included within the control apparatus are conditioned by the states of the predetermined bit positions of the locations to generate output signals to the processing unit enabling the transfer of requested instruction words to the processing unit as soon as they are received from main store.
27 Citations
39 Claims
-
1. A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:
-
instruction address register means coupled to said data processing unit, said instruction address register means including a number of bit positions for storing an address in response to a predetermined type of said commands previously received from said data processing unit, said address specifying a next instruction word to be accessed by said data processing unit; an addressable instruction buffer coupled to said main store and to said instruction address register means, said instruction buffer comprising a number of sections, each section comprising; a plurality of addressable locations for storing a sequence of instruction words received from said main store, each location including a plurality of bit positions for storing an instruction word and at least one bit position connected to switch from a first state to a second state when an instruction word is being written in said location; and
,control means coupled to said instruction address register means, to said processing unit to said main store and to each of said sections of said instruction buffer, said control means being operative in response to a signal corresponding to said second state received from said one bit position of one of said locations specified by said instruction address register means to generate an output signal to said processing unit, said signal indicating that said next instruction word specified by said instruction address register means has been received from said main store and is being written into one of said buffer locations of one of said sections thereby enabling said processing unit to begin immediately the processing of said next instruction specified by said instruction address register means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled to said cache unit in response to a plurality of different types of commands received from said data processing unit, said cache unit comprising:
-
instruction address register means including a number of bit positions for storing an address in response to a first predetermined type of one of said commands previously received from said data processing unit, said address specifying from which a next instruction word is to be accessed by said data processing unit; an addressable instruction buffer coupled to said main store and to said instruction address register means, said instruction buffer comprising; a first section comprising a plurality of addressable locations for storing a first sequence of instruction words received from said main store, each location including a plurality of bit positions for storing an instruction word and at least another bit position for storing a first instruction buffer valid indication for signalling when said instruction word has been written in said location; a second section comprising a plurality of locations for storing a second sequence of instruction words received from said main store, each location including a plurality of bit positions for storing an instruction word and at least another bit position for storing a second instruction buffer valid indication for signalling when said instruction word is being written into said location; and
,control means for controlling the operation of said instruction buffer, said control means being coupled to said instruction address register means, to said first section, to said second section and to said processing unit, said control means comprising; means operative in response to each first and second predetermined types of commands specifying a transfer of a sequence of instructions from said main store to generate reset signals for initializing each of said plurality of locations of said first and second sections respectively to a first state; and
,instruction buffer ready control logic means coupled to said instruction buffer for receiving signals corresponding to said first and second instruction valid indications read out from the locations specified by said instruction address register means, to said main store for receiving signals identifying the instruction word being transferred to one of said sections and to said instruction address register means for receiving signals identifying said next instruction within one of said instruction sequences to be accessed by said processing unit, said instruction ready control logic means being operative in response to said signals from said buffer, said instruction address register means and said main store to generate an output signal upon detecting that said next instruction word has been received and is being written into one of the locations of said buffer enabling its immediate transfer to said data processing unit. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
-
-
26. A cache system for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled to said cache system, in response to commands from said data processing unit, said cache system comprising:
-
an instruction address register including a number of bit positions for storing control information and an address in response to a predetermined one of said commands from said data processing unit, said address specifying a next instruction word to be accessed by said data processing unit; a first addressable instruction buffer coupled to said main store and to said instruction address register means, said buffer having a plurality of data input terminals for receiving instruction words from said main store, said first instruction buffer comprising; a plurality of addressable locations for storing a first sequence of said instruction words, each location including a plurality of bit positions for storing an instruction word and at least another bit position for storing a predetermined indication when said instruction word is being written into said location; a second addressable instruction buffer coupled to said main store and to said instruction address register means, said buffer having said plurality of data input terminals for receiving said instruction words from said main store, said second buffer comprising; a plurality of addressable locations for storing a second sequence of said instruction words, each location including a plurality of bit positions for storing an instruction word and at least said another bit position for storing said predetermined indication when said instruction word is being written into said location; and
,control means coupled to said instruction address register, to said processing unit and individually to said first and second instruction buffers, said control means being operative in response to a signal corresponding to said predetermined indication read out from one of said locations specified by said instruction address register means to generate an output signal to said processing unit, said signal indicating that said instruction word specified by said instruction address register means has been transferred by said main store in response to a predetermined type of one of said commands applied to said cache unit by said data processing unit and is being written into one of said locations of said instruction buffer designated in accordance with the coding of said predetermined type of command. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
-
Specification