Tuning apparatus

• US 4,312,044 A
• Filed: 02/06/1979
• Issued: 01/19/1982
• Est. Priority Date: 02/17/1978
• Status: Expired due to Term

• Current Assignee: Nippon Yusen Kabushiki Kaisha
• Original Assignee: Nippon Yusen Kabushiki Kaisha
• Inventors: Baba, Michiru
• Primary Examiner(s): Krass, Errol A.
• Application Number:
  US06/009,950
• Time in Patent Office: 1,078 Days
• Field of Search: 364/554, 364/484, 364/575, 235/92 FQ, 84/DIG. 18, 84/454, 84/458, 84/200, 328/133, 328/141
• US Class Current: 702/106
• CPC Class Codes: G04G 21/02 Detectors of external physical values, e.g. temperature
• CPC Class Codes: G10G 7/02 Tuning forks or like devices
• CPC Class Codes: Y10S 84/18 Tuning

Abstract

Tuning apparatus wherein the instantaneous deviations of a measured sound frequency from a reference sound frequency are averaged to display a mean deviation, thereby to improve the stability of the display. As a display unit, preferably a multidigit segment type display unit is used. The deviation data of the sound is visibly indicated as a positional shift of display elements in the display unit. The tuning apparatus can contain a timepiece therein. A reference frequency oscillating source and the display unit are used as constituents common to the tuning apparatus and the timepiece, whereby a timepiece-containing tuning apparatus which is small in size and light in weight is realized.

Claims

1. A tuning apparatus comprising circuit means for forming means deviation data and for updating said mean deviation data from instantaneous deviations of a measured sound frequency from a reference frequency, said circuit means comprises:

a counter circuit which provides instantaneous deviation data every fixed time interval,

a first memory circuit which temporarily stores the instantaneous deviation data from said counter circuit,

an adder circuit which receives data read out from said first memory circuit on one input side thereof,

means for halving an addition output from said adder circuit, and

a second memory circuit which temporarily stores the halved addition output for the purpose of indicating the halved addition output of said display means, said adder circuit receiving on the other input side thereof data read out from said second memory circuit and indicated in a preceding display, whereby the mean deviation data which has been updated with the preceding display data and the instantaneous deviation data is derived from said second memory circuit; and

display means for visibly indicating said mean deviation data.

2. A tuning apparatus comprising circuit means for forming mean deviation data and updating said mean deviation data from instantaneous deviations of a measured sound frequency from a reference frequency, and display means for visibly indicating said mean deviation data, said display means being so constructed that a mean deviation in a state in which a tuning is substantially established is indicated by a display element situated at a specified position on a display panel, and that a mean deviation responsive to a sound shift onto a high-pitched sound side or a low-pitched sound side in a state in which the tuning is not substantially established is indicated by a display element situated at a position shifting onto one side or onto the other side respectively from said specified position of said display panel.