Digital encoder-decoder

• US 4,312,070 A
• Filed: 12/07/1979
• Issued: 01/19/1982
• Est. Priority Date: 12/07/1979
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Coombes, Daniel J., Seitz, Martin V.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/101,345
• Time in Patent Office: 774 Days
• Field of Search: 371/37, 371/40, 371/42, 371/43, 371/45, 371/46, 371/47
• US Class Current: 714/762
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A digital encoding and decoding system suited for use in a mobile trunked dispatch communication system capable of error correction, error detection, and detection of loss of synchronization. The encoder comprises a cyclic block encoder, an autosynchronization sequence combiner, a convolutional encoder, and a bit interleaver to encode information to be transmitted. The decoder comprises a bit de-interleaver, a convolutional decoder, an autosynchronization sequence combiner, and a cyclical block decoder to recover the transmitted information and also indicates whether any errors are present in the recovered information.

Claims

1. In a data communications system for the transmission and reception of a data bit stream, the improvement comprising:

an encoder for receiving information and processing said information into the data bit stream to be transmitted, said encoder comprising;

cyclic block encoder means for receiving information and producing an error detectable encoded bit stream corresponding thereto;

encoder storage means having a predetermined autosynchronization sequence stored therein;

said autosynchronization sequence selected to optimize, at a decoder, the generation of errors during an out-of-synchronization condition to enable determination of out-of-synchronization conditions between said encoder and decoder;

encoder combining means for combining said autosynchronization bits from the encoder storage means with the bit stream from said cyclic block encoder means to produce a concatenated bit stream; and

convolutional encoder means for receiving said concatenated bit stream from the encoder combining means and producing an error correctable encoded data bit stream corresponding thereto; and

a decoder for receiving and processing said data bit stream to recover said information, said decoder comprising;

convolutional decoder means for receiving said data bit stream and producing an error corrected bit stream;

decoder storage means having a predetermined sequence of autosynchronization bits stored therein, the predetermined sequence of autosynchronization bits corresponding to the autosynchronization bits stored in said encoder storage means;

decoder combining means for combining said error corrected bit stream from the convolutional decoder means with said autosynchronization bit sequence from the decoder storage means and to provide a block encoded bit stream; and

cyclic block decoder means for decoding said block encoded bit stream to recover said information, said cyclic block decoder means further producing an output indicating the presence of errors in the recovered data bit stream when said decoder is in synchronization with said encoder.

2. The data communications system of claim 1, wherein said data bit stream is comprised of a total of K bits;

said cyclic block encoder means produces an error detectable encoded bit stream of a total of N greater than K bits; and

said convolutional encoder means is a rate one-half convolutional encoder which produces an error correctable encoded data bit stream of 2 times the quantity N+1 bits, where N and K are predetermined integers.

3. The data communications system of claim 2, said encoder further comprising means for interleaving said error correctable encoded bit stream from said convolutional encoder means, and said encoder further comprising means for de-interleaving said recovered data bit stream from said cyclic block decoder means, for enhanced burst error protection.

4. A method for enhancing the transmission and reception of data in a digital communications system comprising the steps of encoding a data bit stream by:

error detection encoding said data bit stream with a cyclic block encoder to produce an error detectable bit stream;

combining a predetermined sequence of autosynchronization bits, selected to optimize the generation of errors detected in an error detection decoding step for an out-of-synchronization condition, with said error detectable bit stream, thereby producing a concatenated bit stream;

error correction encoding said concatenated bit stream with a convolutional encoder to produce an error correctable encoded bit stream; and

decoding said bit stream by;

decoding the convolutional encoding of said bit stream with a convolutional decoder to correct errors and produce an error corrected bit stream;

combining a predetermined sequence of autosynchronization bits, corresponding to the sequence of autosynchronization bits used by the encoder with said error corrected bit stream, to produce a block encoded signal having decodable cyclic block codes; and

decoding the cyclic block encoding of said error corrected bit stream with a cyclic block decoder to detect errors and produce a decoded data bit stream and an error detect signal when the encoding steps at the encoder are in synchronization with the decoding steps at the decoder.

5. The method of claim 4, wherein said data bit stream is comprised of a total of K bits and wherein;

the step of error detection encoding includes a step of cyclic block encoding said K bit data bit stream to produce an encoded error detectable bit stream comprised of a total of N greater than K bits;

the step of error correction encoding includes a step of convolutional encoding said N bit error detectable bit stream to produce a rate one-half convolutional error correctable encoded bit stream comprised of a total of 2 times the quantity N+1 bits, where N and K are predetermined integers;

the step of decoding the convolutional encoding of said bit stream includes a step of convolutional decoding said rate one-half convolutional error correctable encoded bit stream of 2 times the quantity N+1 bits to produce said N bit error detectable bit stream; and

the step of decoding the cyclic block encoding includes a step of cyclic block decoding said N bit encoded error detectable bit stream to produce said K bit data stream.

6. The method of claim 4 wherein;

the steps of encoding said data bit stream further comprises a step of interleaving the bits of said error correctable encoded bit stream after the step of error correction encoding; and

the steps of decoding said data bit stream further comprises a step of de-interleaving the bits of said bit stream prior to the step of decoding the convolutional encoding of the bit stream.

7. In a trunked dispatch system for mobile radio communication using a digital control channel between an encoder for encoding data for transmission on said digital control channel of said trunked dispatch system, and a decoder for receiving and processing the encoded data transmitted on said control channel to recover the data, said encoder comprising:

cyclic block encoder means for receiving the data for transmission on said digital control channel and producing an error detectable cyclic block code corresponding thereto;

storage means for having an autosynchronization frame stored therein, said autosynchronization frame selected to optimize the generation of errors at the decoder caused by an out-of-synchronization condition between said encoder and decoder;

modulo-2 adder means for performing a bit-by-bit exclusive-OR of said error detectable block code and said autosynchronization frame and producing a modulo-2 sum;

rate one-half convolutional encoder means for encoding the modulo-2 sum and producing a bit sequence including the modulo-2 sum bits, a flush-out bit, and parity bits; and

bit interleaving means for reordering the bits in the output of said convolutional encoder to produce an interleaved bit sequence.

8. The trunked dispatch system in claim 7, wherein said block code generated by said block encoder means consists of a (37, 27) shortened cyclical code;

said storage means of said encoder having said autosynchronization frame consists of 37 bits;

said sequence generated by said convolutional encoder means consists of 76 bits;

said interleaved bit sequence is ordered such that if the modulo-2 sum bits are consecutively numbered from 0 to 36 and the parity bits are consecutively numbered from 0 to 37, as they are generated by said rate one-half convolutional encoder, the interleaved sequence will consist of the even numbered modulo-2 sum bits I₀ through I₃₆, followed by even numbered parity bits P₀ through P₃₆, followed by the odd numbered modulo-2 sum bits I₀ through I₃₅ and said flush-out bit, followed by the odd numbered parity bits P₁ through P₃₇.

9. In a trunked dispatch system for a mobile radio communication using a digital control channel between an encoder for encoding data for transmission on said digital control channel and a decoder for receiving and processing the data transmitted on said control channel to recover the data, the decoder comprising;

de-interleaving means for receiving said encoded data and producing an error correctable bit sequence;

rate one-half convolutional decoder means for decoding said error correctable bit sequence and producing an error corrected bit sequence;

storage means for having an autosynchronization frame stored therein;

modulo-2 adder means for performing a bit-by-bit exclusive-OR of said error corrected bit sequence and the stored autosynchronization frame to produce a decoded modulo-2 sum; and

cyclic block decider means for receiving said decoded modulo-2 sum and producing decoded data bits and an error detect signal.

10. The trunked dispatch system in claim 9, wherein said decoder consists of said bit de-interleave means for receiving a 76 bit sequence;

said de-interleaved circuit wherein if said 76 bit sequence is consecutively labeled A₀, B₀, C₀, D₀ ;

A₁, B₁, C₁, D₁ ; and

so on, the de-interleave circuit generates the sequence A₀, A₁, through A₁₈ ;

B₀, B₁, through B₁₈ ;

C₀, C₁, through C₁₈ ;

D₀, D₁, through D₁₈ ;

said convolutional decoder error corrects the 76 bit output of said de-interleave circuit and produces a 37 bit error corrected code sequence;

said storage means of said decoder has said autosynchronization frame consisting of 37 bits; and

said cyclical block decoder decodes a (37,

     27) shortened cyclical code.