Method of manufacturing submicron channel transistors

• US 4,313,782 A
• Filed: 11/14/1979
• Issued: 02/02/1982
• Est. Priority Date: 11/14/1979
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: RCA Corporation
• Inventors: Sokoloski, Joseph C.
• Primary Examiner(s): Massie, Jerome W.
• Application Number:
  US06/094,215
• Time in Patent Office: 811 Days
• Field of Search: 156/628, 156/643, 156/653, 156/657, 156/662, 156/659.1, 156/661.1, 29/571, 148/187, 427/94, 427/399, 357/54, 357/59
• US Class Current: 438/591
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

A method for fabricating a submicron short channel MOS device is described wherein a plural or multilevel insulator layer, having a thickness of about 100-200 angstroms, is interposed between the polycrystalline silicon gate member and the substrate to function as a gate insulator and in addition, serving to protect the body of the semiconductor from becoming inadvertently doped during the processing steps.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor body having a boundary surface;

growing a first layer of oxide on the boundary surface;

depositing a layer of silicon nitride on the oxide layer;

growing a second layer of silicon oxide on the nitride layer;

depositing a layer of polycrystalline silicon on the oxide layer;

depositing a layer of apertured masking material on the polycrystalline silicon layer;

etching unmasked portions of the polycrystalline silicon layer to expose the unetched edges of the polycrystalline silicon material under the masking layer;

doping the exposed edges of the unetched polycrystalline silicon layer to form a narrow line of doped polycrystalline silicon in the polycrystalline silicon layer, the doping step forming a doped oxide on the apertured masking material and exposed second oxide layer;

etching the doped oxide, the apertured masking material, and the exposed portions of the plural level insulator layer to expose the doped and undoped portions of the polycrystalline silicon layer and unmasked portions of the silicon body;

forming a second masking layer over the doped and undoped portions of the polycrystalline silicon layer and over the exposed portions of the silicon body;

forming a third apertured masking layer over selected portions of the second masking layer to mask at least the doped portions of the polycrystalline silicon layer and the exposed portions of the silicon body;

etching the exposed portions of the second masking layer to expose only the undoped portions of the polysilicon layer;

selectively etching the undoped portions of the polycrystalline silicon layer;

removing the second and third masking layers to expose the masked portions of the silicon body and the plural insulator layer; and

removing the remaining exposed portions of the plural insulator layer.

2. The method in accordance with claim 1 comprising the further steps of:

providing a substrate of insulative material selected from the group consisting of sapphire, monocrystalline beryllium and spinel; and

forming the silicon body on the insulative substrate.

3. The method in accordance with claims 1 or 2, in which:

the first and second layers of oxide and the nitride layer have a total thickness of about 100-200 angstroms.

4. The method in accordance with claim 3, in which:

the first oxide layer is a thermally grown silicon oxide having a thickness of about 50-100 angstroms.

5. The method in accordance with claim 4, in which:

the silicon nitride layer has a thickness of about 50-100 angstroms; and

the second silicon oxide layer has a thickness of about 15-20 angstroms.