Digital radio communications system with high noise immunity

• US 4,314,371 A
• Filed: 08/17/1979
• Issued: 02/02/1982
• Est. Priority Date: 08/17/1979
• Status: Expired due to Term

• Current Assignee: Edward L. Covington, Herman D. Self
• Original Assignee: Edward L. Covington, Herman D. Self
• Inventors: Self, Herman D., Covington, Edward L.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US06/067,709
• Time in Patent Office: 900 Days
• Field of Search: 375/58, 375/21, 375/22, 455/31, 455/38, 455/50, 455/63, 455/70, 340/311, 340/171 PF, 340/167, 340/171 R, 340/359, 340/360, 340/168 B
• US Class Current: 375/285
• CPC Class Codes: H03M 5/00 Conversion of the form of the representation of individual digits
• CPC Class Codes: H04W 88/026 using digital address codes

Abstract

A digital data radio transmission system, such as may be used in communicating point-to-point by radio, in which a keyboard is used to insert a multi-decimal-digit number representing the called station. This is fed to a decimal-to-binary converter, forming a train of binary bits which are then coded in a selected manner so as to be substantially noise immune. The output of the coder then goes to the radio transmitter. At the receiving end, a similar means is provided for obtaining and storing in a 24-bit register the selected number of the called station. The output of the radio detector is then decoded to obtain the 24-bit word representing the called station, which is stored in a second register. A comparator compares the numbers stored in the two registers. When they compare positively, an alarm signal is enabled, or the receiver squelch is broken.

Claims

1. A radio transmitting system using a noise minimizing code, for selective calling of radio systems, using a selected multibit sequential binary word having a selected number of binary bits, such as 24, for example;

and register means for storing said 24 bits;

comprising

(a) means for coding said word of 24 sequential binary bits into a coded transmission of clocked trains of binary signal pulses, where each binary signal pulse of said binary signal comprises a square pulse of selected magnitude, polarity and duration D, followed by a space of equal duration D; and

wherein

(b) for each bit of said 24 binary bits which is a logical one, first means to produce a train of a selected number M of said binary signal pulses; and

for each bit of said 24 binary bits which is a logical zero, second means to produce a train of a selected number N of binary signal pulses;

where N is substantially different from M;

(c) between the end of a first train of said binary pulses and the beginning of the next train, means for providing a clocked time space of zero signal equal in length to the length of P binary signal pulses, where P is less than M or N; and

(d) means to modulate a radio transmitter with said coded transmission.

2. The apparatus as in claim 1 in which said first train and said train together comprise a word, and including;

(e) between the end of a first word and the beginning of the next word, means for providing a clocked time space of zero signal equal in length to the length of a selected number R of binary signal pulses, where R is greater than P.

3. The apparatus as in claim 1 in which said 24 binary bit word is derived from a multi-decimal-digit selected word;

and including;

(a) means for providing said multi-decimal-digit word; and

(b) means for deriving from said multi-decimal-digit word said 24 binary bit word.

4. The apparatus as in claim 3 and including:

(a) a calculator chip responsive to said multi-decimal-digit word to provide a 7-segment number corresponding to each decimal digit;

(b) means for converting said 7-segment numbers to binary coded decimal configuration; and

(c) means to store the output of said 7-segment conversion means in a 24 bit serial-in, parallel-out register.

8. The apparatus as in claim 1 in which said first means comprises;

(a) clock means of selected frequency of pulses, and first gate means to transmit said clock pulses to said radio transmitter;

(b) first counter means for counting said clock pulses, said first counter means providing an output signal when M clock pulses have been counted;

(c) third means responsive to said register, and to said first counter means to control said first gate means to start said transmission of clock pulses, and to stop said transmission after M clock pulses have been transmitted;

(d) fourth means responsive to said register and to said first counter means to control said first gate means to start said transmission of clock pulses, and to stop said transmission after N clock pulses have been transmitted;

and

(e) fifth means responsive to said first counter means and to said third and fourth means to control said first gate means to stop said transmission of clock pulses at the end of a train of M pulses or N pulses, for a period of P clock pulses.

9. The apparatus as in claim 1 in which M equals 6, N=12, and P=4.

5. A radio receiving system using a noise minimizing code for selective calling of radio stations, in which the coded transmission comprises a series of 24 binary bits, for example, converted to clocked digital signal pulses in which each digital signal pulse comprises a square positive half-cycle of selected time duration D and a following space of equal time duration D, comprising;

(a) a 24-bit first register for storing the binary word corresponding to the selected radio receiving station;

(b) means to receive the coded transmission calling said selected receiving station;

(c) means to decode said coded transmission to form a 24-bit received binary word, and a second 24-bit register means to store said 24-bit received binary word;

(d) means to compare said 24-bit words in said first and second registers; and

(e) means responsive to said means to compare to enable a ringing signal when said comparison is positive and

in which said means to decode said coded transmission of digital signal pulses, comprises;

(f) first means to count the number of digital signal pulses in a train; and

second means to determine the end of a train of digital pulses; and

counter means responsive to said first and second means;

(g) third means responsive to said counter means to determine if a sufficient number of digital signals have been received to comprise a valid signal;

(h) fourth means responsive to said counter means to determine whether the number of digital signal pulses in a train correspond to a binary one bit or a binary zero bit; and

(i) fifth means responsive to said third and fourth means to clock into said second 24 bit register said determined binary bit.

6. In a radio communication system for calling a selected radio receiver using a binary word indicative of the address of a selected receiver said binary word composed of a selected number B of sequential binary bits, which may be ones or zeros;

improved apparatus for coding said binary bits for noise immune transmission by radio, comprising;

(a) means for providing a series of clocked trains of digital pulses, wherein each digital pulse comprises a square pulse of logic level one and of time duration D, followed by a space of logical level zero and of time duration D;

(b) for each bit of said binary word which is a logical one, means to produce a train of a selected number M of digital pulses; and

for each bit of said binary word which is a logical zero, means to produce a train of a selected number N of digital pulses, where N can be greater than, or less than M, in a ratio of the order of approximately 2 to 1;

(c) between the end of a first train of said digital pulses, and the beginning of the next train, means for providing an interbit space of zero signal level, comprising a clocked space equal to 2PD units of time, where P is a selected integer less than the smaller of M or N; and

(d) means to modulate a radio transmitter in accordance with said series of trains of digital signal pulses.

7. The apparatus as in claim 6, and including after the end of said trains of digital signal pulses corresponding to said B sequential binary bits, means for providing a clocked train of digital signal pulses corresponding to a selected number of binary bits.