Interface between a microprocessor chip and peripheral subsystems

• US 4,315,308 A
• Filed: 12/21/1978
• Issued: 02/09/1982
• Est. Priority Date: 12/21/1978
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jackson, Daniel K.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US05/972,007
• Time in Patent Office: 1,146 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/33
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

An interface between a microprocessor chip and input/output, and memory modules. The interface uses a single, bidirectional bus comprised of a number of lines which is less than the number necessary to carry a complete address word or a full width data word. Information transfer is effected by transferring information in small portions utilizing two or more interface clock cycles. An encoded control specification placed on the bus during the first cycle of information transfer specifies the type of access, the direction of transfer, and the length (number of bytes) of data to be moved. Only two additional simplex lines, one from the microprocessor and the other to the microprocessor are needed to complete the basic interface.

Claims

1. A bus interface unit for use in combination with a microprocessor interface of the type having

a bidirectional multiline bus for carrying address bits, control bits and data bits, said bus having a total number of lines which is less than the total number of bits comprising said address;

an output line (ISA);

an input line (ISB);

means connected to said bus, operative during a first cycle for placing a first number of bits of said address on a first number of said bus lines, and a control specification specifying the direction of data transfer and the amount of data to be transferred, said control specification being placed on a second number of said bus lines; and

,

means connected to said bus operative during a second cycle following said first cycle for placing a second number of bits of said address on said first number and said second number of said bus lines, said data transfer to take place, to or from a location specified by said address, during cycles subsequent to said first and second cycles;

said bus interface unit comprising;

logic means connected to said output line (ISA) and to said first number and said second number of said bus lines, said logic means including first and second address registering means, said logic means operative in response to said output line (ISA) and to said first number of bits of said address on said first number of bus lines and to said control specification of said second number of bus lines, during said first cycle, for decoding said control specification and for registering said first number of bits of said address, in said first address registering means, said logic means being further operative in response to said output line (ISA) during said second cycle for registering said second number of bits of said address, in said second address registering means, whereby a complete address comprised of said first and second number of bits is registered by the end of said second cycle;

first means connected to said logic means and to said multiline bus for controlling the direction of said data transfer on said multiline bus; and

,

second means connected to said logic means and to said multiline bus for controlling the amount of data transferred on said multiline bus,

said first and second controlling means being operative in accordance with control information contained in said control specification.

2. The bus interface unit in accordance with claim 1 further comprising:

means included in said logic means and connected to said output line (ISA), operative during a decoded read and a decoded write operation specified by said control information for asserting said input line (ISB) in each cycle subsequent to said second cycle to thereby indicate to said microprocessor interface that valid data has been placed on said bus during a read operation and to indicate that data has been accepted during a write operation.

3. The bus interface unit in accordance with claim 1 wherein said bus interface unit is capable of being connected to a memory module in which data may be accessed at said address, said bus interface unit further comprising:

a memory address bus for connecting said bus interface unit to said memory module; and

means connecting said first and second address registering means to said memory address bus for providing, to said memory module, said complete memory address comprised of said first number of bits and said second number of bits of said address.

4. The bus interface unit in accordance with claim 3 wherein said first and second address registering means in combination comprise a loadable counter, said loadable counter capable of being incremented in response to energization of an increment input thereto,

said logic means further including means for decoding said control specification specifying the amount of data to be transferred and means for energizing said increment input to said loadable counter, whereby sequential memory addresses may be provided to said memory address bus in accordance with the amount of data to be transferred specified in said control specification.

5. An interface logic for use in combination with a microprocessor having

a single, bidirectional, multiline bus comprised of a number of lines which is less than the number of lines necessary to carry a complete address word;

a first simplex line;

a second simplex line;

means connected to said multiline bus, operative during a first cycle for placing a first number of bits of said address on a first number of said bus lines, and an encoded control specification, said control specification specifying the direction of data transfer and the amount of data to be transferred, said control specification being placed on a second number of said bus lines; and

,

means connected to said multiline bus, operative during a second cycle following said first cycle, for placing a second number of bits of said address on said first number and said second number of said bus lines, said data transfer to take place to or from a location specified by said address, during cycles subsequent to said first and second cycles;

said interface logic comprising;

first means for receiving from said microprocessor said encoded control specification on said bus during said first cycle of information transfer between said microprocessor and said interface logic over said bus, said control specification specifying the type of access, the direction of transfer, and the length of data to be moved;

second means connected to said first simplex line (ISA) from said microprocessor, responsive to said first simplex line during a cycle subsequent to said first cycle for indicating to said interface logic that a bus transaction is underway;

third means for energizing said second simplex line (ISB) into said microprocessor, said second simplex line (ISB) being energizable to indicate, when in a first state, that valid data has been placed on said bus by said interface logic, and, when in a second state, that valid data has been accepted from said bus by said interface logic, respectively, during a read operation or a write operation;

said first means for receiving further comprising an address register including a first portion and a second portion; and

,

fourth means responsive to signals on said bus for gating a first number of said bus lines to said first portion of said address register during said first cycle of operation of said bus,

said fourth means including fifth means for gating a second number of said bus lines to said second portion of said address register during a cycle of operation of said bus subsequent to said first cycle;

whereby a complete address may be constructed sequentially during successive cycles of operation of said bidirectional bus.

6. The interface logic in accordance with claim 5 wherein said first means for receiving an encoded control specification comprises:

means connected to said bidirectional bus for detecting a predetermined pattern of energization of said bidirectional bus lines, and

means operative upon detection of said pattern for starting said first cycle of information transfer on said bus.

7. The interface logic in accordance with claim 5 further comprising:

a memory module;

a memory address bus connected to said memory module and to said address register;

read and write logic means connected between said bidirectional bus and said memory module for controlling the direction of data transfer between said bidirectional bus and said memory module; and

,

wherein said means for receiving an encoded control specification includes means for decoding said control specification to provide signals to said memory module, to said address register, and to said read and write logic means, to control, respectively, the type of access, the direction of data transfer between said bidirectional bus and said memory module, and the length of data to be moved.

8. The interface logic in accordance with claim 7 wherein said address register comprises a loadable counter, and said means for receiving an encoded control specification includes means for decoding said control specification to provide a signal for incrementing said counter to provide sequential addresses to said memory module over said memory address bus, said addresses corresponding to sequential bytes of data being moved between said bidirectional bus and said memory module.

9. The interface logic in accordance with claim 5 wherein said means for receiving an encoded control specification includes further means responsive to energization of said second simplex line (ISB) for generating cycles of a read or write operation wherein said second simplex line (ISB) has status significance other than that valid data has been placed on said bus or accepted from said bus, respectively, during said read or write operation.